TB28F004S3-150 Intel, TB28F004S3-150 Datasheet - Page 31

• Manufacturer Part Number: TB28F004S3-150
• Manufacturer: Intel

Specifications of TB28F004S3-150

• Density: 4Mb
• Access Time (max): 150ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

6.4
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal V
2. I
3. Includes RY/BY#.
4. Block erases, program, and lock-bit configurations are inhibited when V
5. Automatic Power Savings (APS) reduces typical I
6. CMOS inputs are either V
7. Sampled, not 100% tested.
8. Master lock-bit set operations are inhibited when RP# = V
9. RP# connection to a V
V
V
V
V
V
V
V
V
V
V
Sym
IL
IH
OL
OH1
OH2
PPLK
PPH1
PPH2
LKO
HH
valid for all product versions (packages and speeds).
current is the sum of I
between V
master lock-bit is set and RP# = V
and RP# = V
attempted with V
PRELIMINARY
CCWS
and I
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
(TTL)
Output High Voltage
(CMOS)
V
V
V
V
RP# Unlock Voltage
DC Characteristics— Commercial Temperature
PP
PP
PP
CC
PPLK
CCES
Lockout Voltage
Voltage
Voltage
Lockout Voltage
IH
. Block erase, program, and lock-bit configuration operations are not guaranteed and should not be
(max) and V
Parameter
are specified with the device de-selected. If read or written while in erase suspend mode, the device’s
IH
< RP# < V
CCWS
HH
supply is allowed for a maximum cumulative period of 80 hours.
CC
or I
PPH1
± 0.2 V or GND ± 0.2 V. TTL inputs are either V
HH
CCES
.
(min), between V
IH
and I
. Block erases and program are inhibited when the corresponding block-lock bit is set
Notes Min
CCR
3,7
3,7
3,7
4,7
8,9
7
7
or I
CCW
–0.5
0.85
–0.4
V
V
2.7 V V
2.0
2.4
2.7
2.0
PPH1
CCR
CC
CC
.
to 3 mA at 3.3 V V
(max) and V
+ 0.5
Max
V
0.8
0.4
1.5
3.6
IH
CC
CC
. Block lock-bit configuration operations are inhibited when the
–0.5
0.85
–0.4
11.4
11.4
Min
V
V
3.3 V V
2.0
2.4
2.7
2.0
CC
CC
PPH2
PP
(min), and above V
+ 0.5
CC
Max Unit
12.6
12.6
V
0.8
0.4
1.5
3.6
CC
CC
in static operation.
CC
V
IL
PPLK
or V
voltage and T
28F004S3/28F008S3/28F016S3
(Continued)
V
V
V
V
V
V
V
V
V
V
V
, and not guaranteed in the range
IH
.
V
I
V
I
V
I
V
I
Set Master Lock-Bit
Override Lock-Bit
OL
OH
OH
OH
CC
CC
CC
CC
= 2 mA
PPH2
= –2.5 mA
= –2.5 mA
= –100 µA
= V
= V
= V
= V
A
= +25 C. These currents are
(max).
CC
CC
CC
CC
Conditions
Min
Min
Min
Min
Test
31