TB28F004S3-150 Intel, TB28F004S3-150 Datasheet - Page 17

• Manufacturer Part Number: TB28F004S3-150
• Manufacturer: Intel

Specifications of TB28F004S3-150

• Density: 4Mb
• Access Time (max): 150ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error is
detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to “1.” Also,
reliable block erasure can only occur when
V
this high voltage, block contents are protected
against erasure. If block erase is attempted while
V
Successful
corresponding block lock-bit be cleared or, if set,
that RP# = V
the corresponding block lock-bit is set and
RP# = V
SR.5 will be set to “1.” Block erase operations with
V
should not be attempted.
4.6
Program is executed by a two-cycle command
sequence.
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the program and verify algorithms
internally. After the program sequence is written,
the device automatically outputs status register
data when read (see Figure 8). The CPU can detect
the completion of the program event by analyzing
the RY/BY# pin or status register bit SR.7.
When program is complete, status register bit SR.4
should be checked. If program error is detected, the
status register should be cleared. The internal WSM
verify only detects errors for “1”s that do not
successfully program to “0”s. The CUI remains in
read status register mode until it receives another
command.
Reliable program only occurs when V
V
memory contents are protected against program
operations. If a program operation is attempted
while V
register bits SR.3 and SR.5 will be set to “1.”
CC
PP
IH
PP
PRELIMINARY
< RP# < V
= V
= V
PP
V
PPH1/2
CC2
PPLK
IH
Program Command
, the block erase will fail, and SR.1 and
V
Program setup (standard 40H
and V
, SR.3 and SR.5 will be set to “1.”
HH
PPLK
block
. In the absence of this high voltage,
. If block erase is attempted when
HH
, the operation will fail, and status
PP
produce spurious results and
erase
= V
PPH1/2
requires
. In the absence of
CC
= V
that
CC2
and
the
or
A successful program operation also requires that
the corresponding block lock-bit be cleared or, if
set, that RP# = V
attempted when the corresponding block lock-bit is
set and RP# = V
and SR.4 will be set to “1.” Program operations with
V
should not be attempted.
4.7
The Block Erase Suspend command allows
block-erase interruption to read or program data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs status register
data when read after the Block Erase Suspend
command is written. Polling status register bits
SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to
“1”).
Specification t
suspend latency.
At this point, a Read Array command can be written
to read data from blocks other than that which is
suspended. A Program command sequence can
also be issued during erase suspend to program
data in other blocks. Using the Program Suspend
command (see Section 4.8), a program operation
can also be suspended. During a program operation
with block erase suspended, status register bit
SR.7 will return to “0” and the RY/BY# output will
transition to V
indicate block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and RY/BY# will return to V
Resume
automatically outputs status register data when
read (see Figure 9). V
(the same V
block erase is suspended. RP# must also remain at
V
erase). Block erase cannot resume until program
operations initiated during block erase suspend
have completed.
IH
IH
< RP# < V
or V
RY/BY#
HH
Block Erase Suspend
Command
command
(the same RP# level used for block
PP
OL
28F004S3/28F008S3/28F016S3
WHRH2
. However, SR.6 will remain “1” to
level used for block erase) while
IH
HH
will
, the operation will fail, and SR.1
HH
produce spurious results and
. If a program operation is
also
defines the block erase
PP
is
must remain at V
written,
transition
OL
. After the Erase
the
to
device
PPH1/2
V
OH
17
.