CYNSE70064A-66BGC Cypress Semiconductor Corp, CYNSE70064A-66BGC Datasheet - Page 11

• Manufacturer Part Number: CYNSE70064A-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-66BGC

• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.9V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

4.4
Pipeline latency is added to give enough time to a cascaded system’s arbitration logic to determine the device that will drive the
index of the matching entry on the SRAM bus. Pipeline logic adds latency to both the SRAM access cycles and the SSF and SSV
signals to align them to the host ASIC receiving the associated data.
4.5
Bit[0] in each of the 68-bit entries has a special purpose for the Learn command (0 = empty, 1 = full). When all the data entries
have bit[0] = 1, the database asserts the FULL flag, indicating that all the search engines in the depth-cascaded array are full.
5.0
Table 5-1 lists and describes all CYNSE70064A signals.
Table 5-1. CYNSE70064A Signal Description
Document #: 38-02041 Rev. *F
Clocks and Reset
CMD and DQ Bus
SRAM Interface
Notes:
1.
2.
3.
4.
I = Input only, I/O = Input or Output, O = Output only, T = three-state output.
PIO = Programmed Input/Output.
ACK and EOT require a weak external pull-down such as 47KΩ or 100KΩ.
CLK” is an internal clock signal. Any reference to “CLK cycles” means one cycle of CLK.
SADR[21:0]
Parameter
CMD[8:0]
DQ[67:0]
CLK2X
PHS_L
RST_L
CMDV
ACK
EOT
Pipeline and SRAM Control
Full Logic
CE_L
Signal Descriptions
SSF
SSV
[4]
[4]
Type
I/O
T
T
T
T
T
T
I
I
I
I
I
[1]
Master Clock. CYNSE70064A samples all the data and control pins on the positive edge of
CLK2X. All signals are driven out of the device on the rising edge of CLK2X (when PHS_L is
LOW).
Phase. This signal runs at half the frequency of CLK2X and generates an internal CLK
CLK2X. See Section 6.0, “Clocks” on page 13.
Reset. Driving RST_L LOW initializes the device to a known state.
CMD Bus. [1:0] specifies the command and [8:2] contains the CMD parameters. The descrip-
tions of individual commands explains the details of the parameters. The encoding of
commands based on the [1:0] field are:
00: PIO
01: PIO Write
10: Search
11: Learn.
CMD Valid. This signal qualifies the CMD bus:
0: No command
1: Command.
Address/Data Bus. This signal carries the Read and Write address and data during register,
data, and mask array operations. It carries the compare data during Search operations. It also
carries the SRAM address during SRAM PIO accesses.
Read Acknowledge. This signal indicates that valid data is available on the DQ bus during
register, data, and mask array Read operations, or that the data is available on the SRAM
data bus during SRAM Read operations.
End of Transfer. This signal indicates the end of burst transfer to the data or mask array
during Read or Write burst operations.
Search Successful Flag. When asserted, this signal indicates that the device is the global
winner in a Search operation.
Search Successful Flag Valid. When asserted, this signal qualifies the SSF signal.
SRAM Address. This bus contains address lines to access off-chip SRAMs that contain
associative data. See Table 12-1 for the details of the generated SRAM address. In a
database of multiple CYNSE70064As, each corresponding bit of SADR from all cascaded
devices must be connected.
SRAM Chip Enable. This is the chip-enable control for external SRAMs. In a database of
multiple CYNSE70064As, CE_L of all cascaded devices must be connected. This signal is
then driven by only one of the devices.
[3]
Read
Description
CYNSE70064A
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