CYNSE70064A-66BGC Cypress Semiconductor Corp, CYNSE70064A-66BGC Datasheet - Page 128

• Manufacturer Part Number: CYNSE70064A-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-66BGC

• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.9V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Document History Page
Document #: 38-02041 Rev. *F
Document Title: CYNSE70064A Network Search Engine
Document Number: 38-02041
REV.
*A
*B
*C
*D
*E
*F
**
ECN NO.
123686
126020
289735
116610
118153
119282
111438
Issue Date
See ECN
02/21/02
07/10/02
09/19/02
02/20/03
05/08/03
11/19/02
Change
Orig. of
OOR
OOR
KOS
AFX
AVJ
ITL
ED
New data sheet
Changed every CYNSE70064 to CYNSE70064A
Added Power section covering power-up sequence
Updated JTAG section with the Supported Operations table
Added 83-MSPS part information to Overview, DC Electrical Specifications,
AC Timing Parameters
Added note to Power-up Sequence
Removed CYNSE70128/256-specific instructions
Removed alternative method from power-up sequence instructions
Removed TEST from Signal Description Table 5-1
Added Pin A10 to the pinout descriptions Table 18-1
Added ”Output-T” in the Signal Type field of the Pin E18 Table 18-1
Changed F1 Signal Name and Type from VDDQ to VDD and 3.3V/2.5V to
1.8V Table 18-1
Added “1.8V” in the Signal Type field of Pin F20 Table 18-1
Changed U6 Package Ball Number from U6I/O to U6 Table 18-1
Reordered the pinouts list Table 18-1
Updated Figure 13-1 to reselect the correct waveforms
Corrected the power-up sequence description above the figure
Added a note in the footer explaining PIO
Added explanation about Clock in Section 6 and changed Figure 6-1
Changed the bit number from 283 to 271 for the 272-bit configuration in
Figure 9-1
Added explanation about latency of SSF and SSV
Added explanation about depth cascading in sections 11.1 and 11.2
Added explanation in section 12.2 about data transferred directly between
SRAM and ASIC for SRAM accesses
Added explanation about table ID bits
Added section 12.9 and Table 12-2 about idle cycles between two
successive operations
Description of Change
CYNSE70064A
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