CYNSE70064A-66BGC Cypress Semiconductor Corp, CYNSE70064A-66BGC Datasheet - Page 20

• Manufacturer Part Number: CYNSE70064A-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-66BGC

• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.9V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 10-4. Read Address Format for Data Array, Mask Array, or SRAM
Table 10-5 describes the Read address format for the internal registers. Figure 10-2 illustrates the timing diagram for the burst
Read of the data or mask array.
Table 10-5. Read Address Format for Internal Registers
Note:
Document #: 38-02041 Rev. *F
DQ[67:30] DQ[29]
6.
Reserved 0: Direct
Reserved 0: Direct
Reserved 0: Direct
“ | ” stands for logical OR operation. “{}” stands for concatenation operator.
DQ[67:26]
Reserved
1: Indirect
1: Indirect
1: Indirect
CMD[8:2]
CMD[1:0]
CLK2X
PHS_L
CMDV
ACK
SSRI (applicable
SSRI (applicable
SSRI (applicable
DQ
if DQ[29] is
if DQ[29] is
if DQ[29] is
DQ[28:26]
indirect)
indirect)
indirect)
DQ[25:21]
ID
Figure 10-1. Single-Location Read Cycle Timing
DQ[25:21] DQ[20:19] DQ[18:15]
ID
ID
ID
cycle
A
Address
1
Read
01: Mask
00: Data
B
External
SRAM
Array
Array
10:
cycle
11: Register
DQ[20:19]
2
Reserved If DQ[29] is 0, this field carries the address of the data
Reserved If DQ[29] is 0, this field carries the address of the mask
Reserved If DQ[29] is 0, this field carries the address of the SRAM
cycle
3
array location. If DQ[29] is 1, the SSRI specified on
DQ[28:26] is used to generate the address of the data
array location: {SSR[14:2], SSR[1] | DQ[1], SSR[0] |
DQ[0]}.
array location. If DQ[29] is 1, the SSRI specified on
DQ[28:26] is used to generate the address of the mask
array location: {SSR[14:2], SSR[1] | DQ[1], SSR[0] |
DQ[0]}.
location. If DQ[29] is 1, the SSRI specified on DQ[28:26]
is used to generate the address of the SRAM location:
{SSR[14:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}
cycle
4
FF
[6]
[6]
Reserved
DQ[18:6]
cycle
5
Data
DQ[14:0]
cycle
6
CYNSE70064A
Register Address
DQ[5:0]
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[6]