CYNSE70064A-66BGC Cypress Semiconductor Corp, CYNSE70064A-66BGC Datasheet - Page 15

• Manufacturer Part Number: CYNSE70064A-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-66BGC

• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.9V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

7.4
Table 7-3 describes the command register fields.
Table 7-3. Command Register Description
Document #: 38-02041 Rev. *F
SRST
DEVE
LRAM
LDEV
TLSZ
HLAT
Field
CFG
Command Register
Range Initial Value
[67:17]
[16:9]
[3:2]
[6:4]
[0]
[1]
[7]
[8]
00000000
000
01
0
0
0
0
0
Software Reset. If 1, this bit resets the device with the same effect as a hardware reset.
Internally, it generates a reset pulse lasting for eight CLK cycles. This bit automatically resets
to a 0 after the reset has completed.
Device Enable. If 0, it keeps the SRAM bus (SADR, WE_L, CE_L, OE_L, and ALE_L), SSF,
and SSV signals in three-state condition and forces the cascade interface output signals
LHO[1:0] and BHO[2:0] to 0. It also keeps the DQ bus in input mode. The purpose of this bit is
to make sure that there are no bus contentions when the devices power up in the system.
Table Size. The host ASIC must program this field to configure the chips into a table of a certain
size. This field affects the pipeline latency of the Search and Learn operations as well as the
Read and Write accesses to the SRAM (SADR[21:0], CE_L, OE_L, WE_L, ALE_L, SSV, SSF,
and ACK). Once programmed, the Search latency stays constant.
Latency in number of CLK cycles
00: One device
01: Up to eight devices
10: Up to 31 devices
11: Reserved.
Latency of Hit Signals. This field further adds latency to the SSF and SSV signals during
Search, and ACK signal during SRAM Read access by the following number of CLK cycles.
000: 0 100: 4
001: 1 101: 5
010: 2 110: 6
011: 3 111: 7
This latency depends on the address-in to data-out delay of the SRAM.This needs to be added
to the SSF and SSV signals so that the data from the SRAM, SSF and SSV arrive back to the
ASIC at the same time.
Last Device in the Cascade. When set, this is the last device in the depth-cascaded table and
is the default driver for the SSF and SSV signals. In the event of a Search failure, the device
with this bit set drives the hit signals as follows: SSF = 0, SSV = 1.
During nonSearch cycles, the device with this bit set drives the signals as follows: SSF = 0,
SSV = 0.
Last Device on the SRAM Bus. When set, this device is the last device on the SRAM bus in
the depth-cascaded table and is the default driver for the SADR, CE_L, WE_L, and ALE_L
signals. In cycles where no CYNSE70064A device in a depth-cascaded table drives these
signals, this devices drives the signals as follows: SADR = 22’h3FFFFF, CE_L = 1, WE_L = 1,
and ALE_L = 1. OE_L is always driven by the device for which this bit is set.
Database Configuration. The device is divided internally into four partitions of 8K × 68, each
of which can be configured as 8K × 68, 4K × 136, or 2K × 272, as follows.
00: 8K × 68
01: 4K × 136
10: 2K × 272
11: Reserved
Bits [10:9] apply to configuring the first partition in the address space.
Bits [12:11] apply to configuring the second partition in the address space.
Bits [14:13] apply to configuring the third partition in the address space.
Bits [16:15] apply to configuring the fourth partition in the address space.
Reserved.
4
5
6
Description
CYNSE70064A
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