CYNSE70064A-66BGC Cypress Semiconductor Corp, CYNSE70064A-66BGC Datasheet - Page 26

• Manufacturer Part Number: CYNSE70064A-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-66BGC

• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.9V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 68-bit
searches in ×68-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 68-bit Search command
cycle (two CLK2X cycles) is shown in Table 10-10.
Table 10-10. The Latency of Search from Instruction to SRAM Access Cycle
The latency of a Search from command to SRAM access cycle is 4 for a single device in the table (TLSZ = 00). Different values
of TLSZ add additional delay to SSV and SSF signals. In addition, the latency for SSV and SSF can be further increased
depending on the value of HLAT, as specified in Table 10-11.
Table 10-11. Shift of SSF and SSV from SADR
10.7
The hardware diagram of the Search subsystem of eight devices is shown in Figure 10-8. The following are the parameters
programmed into the eight devices.
Note. All eight devices must be programmed with the same values for TLSZ and HLAT. Only the last device in the table (device
number 7 in this case) must be programmed with LRAM = 1 and LDEV = 1. All other upstream devices (devices 0 through 6 in
this case) must be programmed with LRAM = 0 and LDEV = 0.
Figure 10-9 shows the timing diagram for a Search command in the 68-bit-configured table of eight devices for device number 0.
Figure 10-10 shows the timing diagram for a Search command in the 68-bit-configured table of eight devices for device number 1.
Figure 10-11 shows the timing diagram for a Search command in the 68-bit-configured table of eight devices for device number 7
(the last device in this specific table). For these timing diagrams four 68-bit searches are performed sequentially. Hit/Miss assump-
tions were made as shown below in Table 10-12.
Document #: 38-02041 Rev. *F
• First seven devices (devices 0–6): CFG = 00000000, TLSZ = 01, HLAT = 010, LRAM = 0, and LDEV = 0.
• Eighth device (device 7): CFG = 00000000, TLSZ = 01, HLAT = 010, LRAM = 1, and LDEV = 1.
Number of Devices
1–31 (TLSZ = 10)
1–8 (TLSZ = 01)
68-bit Search on Tables Configured as ×68 Using up to Eight CYNSE70064A Devices
1 (TLSZ = 00)
HLAT
000
001
010
100
101
011
110
111
Comparand Register (odd)
Comparand Register (even)
67
K
K
Figure 10-7. x68 Table with One Device
0
Max Table Size
992K × 68 bits
256K × 68 bits
32K × 68 bits
Location
address
32767
L
0
1
2
3
67
67
(68-bit configuration)
CFG = 00000000
GMR
Number of CLK Cycles
K
0
0
1
2
3
4
5
6
7
0
(First matching entry)
Latency in CLK Cycles
4
5
6
CYNSE70064A
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