TE28F256J3C125 Intel, TE28F256J3C125 Datasheet - Page 35

• Manufacturer Part Number: TE28F256J3C125
• Manufacturer: Intel

Specifications of TE28F256J3C125

• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 125ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 25/24Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 32M/16M
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

9.2
Datasheet
Read Array
Read Identifier Codes
Read Query
Read Status Register
Clear Status Register
Write to Buffer
Word/Byte Program
Block Erase
Block Erase, Program
Suspend
Block Erase, Program
Resume
Configuration
Set Block Lock-Bit
Table 14. Command Bus-Cycle Definitions (Sheet 1 of 2)
Command
Device Commands
When the V
codes, or blocks are enabled. Placing V
and lock-bit configuration operations. Device operations are selected by writing specific
commands into the CUI.
commands.
Scalable or
Command
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
SCS/BCS
Basic
Set
SCS
SCS
SCS
PEN
(2)
voltage ≤ V
Cycles
Req’d.
Bus
> 2
≥ 2
≥ 2
1
2
1
2
2
1
1
2
2
Table 14, “Command Bus-Cycle Definitions” on page 35
PENLK
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
, only read operations from the Status Register, CFI, identifier
(3)
First Bus Cycle
PENH
Addr
BA
BA
X
X
X
X
X
X
X
X
X
X
on V
(4)
PEN
Data
0x40 or
0X90
0xD0
0xFF
0x98
0x70
0x50
0xE8
0x10
0x20
0xB0
0xB8
0x60
additionally enables block erase, program,
(5,6)
Oper
Read
Read
Read
Write
Write
Write
Write
Write
Second Bus Cycle
(3)
Addr
QA
BA
BA
BA
PA
IA
X
X
256-Mbit J3 (x8/x16)
(4)
Data
0xD0
0x01
SRD
defines these
QD
CC
PD
ID
N
(5,6)
1,9, 10,
1,12,13
1,12,14
1,11,12
Notes
1,12
1,7
1,8
11
1
1
1
1
1
35