TE28F256J3C125 Intel, TE28F256J3C125 Datasheet - Page 40

• Manufacturer Part Number: TE28F256J3C125
• Manufacturer: Intel

Specifications of TE28F256J3C125

• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 125ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 25/24Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 32M/16M
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

256-Mbit J3 (x8/x16)
40
WSMS
High Z
Busy?
When
High Z
Busy?
When
Table 18. Status Register Definitions
Table 19. Extended Status Register Definitions
bit 7
WBS
Yes
Yes
Yes
Yes
Yes
Yes
Yes
bit 7
No
Yes
No
SR.7 = WRITE STATE MACHINE STATUS
SR.6 = ERASE SUSPEND STATUS
SR.5 = ERASE AND CLEAR LOCK-BITSSTATUS
SR.4 = PROGRAM AND SET LOCK-BIT STATUS
SR.3 = PROGRAMMING VOLTAGE STATUS
SR.2 = PROGRAM SUSPEND STATUS
SR.1 = DEVICE PROTECT STATUS
SR0 = RESERVED FOR FUTURE ENHANCEMENTS
XSR.7 = WRITE BUFFER STATUS
1 = Write buffer available
0 = Write buffer not available
XSR.6–XSR0 = RESERVED FOR FUTURE
ENHANCEMENTS
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Block Erasure or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
1 = Program Error / Error in Setting Lock-Bit
0 = Successful Program/Set Block Lock Bit
1 = Low Programming Voltage Detected, Operation
0 = Programming Voltage OK
1 = Block Lock-Bit Detected, Operation Abort
0 = Unlock
1 = Program suspended
0 = Program in progress/completed
bit 6
ESS
Aborted
Status Register Bits
Status Register Bits
ECLBS
bit 5
PSLBS
bit 4
VPENS
bit 3
Reserved
Bits 6 -- 0
After a Buffer-Write command, XSR.7 = 1 indicates
that a Write Buffer is available.
SR[6:0] are reserved for future use and should be
masked when polling the Status Register.
Check STS or SR.7 to determine block erase,
program, or lock-bit configuration completion.
SR[6:0] are not driven while SR.7 = “0.”
If both SR.5 and SR.4 are “1”s after a block erase or
lock-bit configuration attempt, an improper
command sequence was entered.
SR.3 does not provide a continuous programming
voltage level indication. The WSM interrogates and
indicates the programming voltage level only after
Block Erase, Program, Set Block Lock-Bit, or Clear
Block Lock-Bits command sequences.
SR.1 does not provide a continuous indication of
block lock-bit values. The WSM interrogates the
block lock-bits only after Block Erase, Program, or
Lock-Bit configuration command sequences. It
informs the system, depending on the attempted
operation, if the block lock-bit is set. Read the block
lock configuration codes using the Read Identifier
Codes command to determine block lock-bit status.
SR0 is reserved for future use and should be
masked when polling the Status Register.
PSS
bit2
Notes
Notes
DPS
bit 1
Datasheet
bit 0
R