TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 102

no-image

TXC-06101AILQ

Manufacturer Part Number
TXC-06101AILQ
Description
Manufacturer
Transwitch Corporation
Datasheet

Specifications of TXC-06101AILQ

Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
PQFP
Rad Hardened
No
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TXC-06101AILQ
Manufacturer:
ATMEL
Quantity:
100
Company:
Part Number:
TXC-06101AILQ A
Quantity:
32
Part Number:
TXC-06101AILQ-A
Manufacturer:
TRANSWITCH
Quantity:
20 000
Notes:
1. If SPE-only mode is selected, this control is disabled. Only the Serial Interfaces are active at Both the Tx and Rx
2. If Pin MBEI is Low, this control is disabled. Only the Parallel Interfaces, operating at 19.44 Mbyte/s, are active at Both
3. If PARA = "1", RCLK = "1" and RETSEL = "0", only the Parallel Interfaces, operating at 6.48 Mbyte/s, are active at Both
Address
Terminal Ports.
the Tx and Rx Terminal Ports.
the Tx and Rx Terminal Ports.
0FA
[H]
Bit
4
3
2
1
0
Proprietary TranSwitch Corporation Information for use Solely by its Customers
Symbol
TRLRDI
ALTOW
TIEN
PIEN
-VE
Tx Line Port Line RDI Enable:
enables automatic insertion of
RDI-L in Tx Line Data. K2 Byte Bits
6-8 controlled by alarm conditions.
Order Wire Mode Control:
OW Frame Pulse at OW/APS Port
coincident with MSB of E1 and E2
Bytes
Transport Layer Interrupt
Enable: enables Transport Layer
Interrupts
Path Layer Interrupt Enable:
enables Path Layer Interrupts
Interrupt Edge Control:
interrupts on both positive and neg-
ative edges of alarms
RLOC
RLOS
RLOF
RAIS-L
B2ELRDI
J0MLRDI
RING
RGRDI-L
TRLRDI
STLRDI
B2EBER
J0MIS
Source K2 Byte
Bits 6, 7, 8
Bit Equal to "1"
=1
=1
=1
&
=1
=1
&
&
/
- 102 of 196 -
Tx Line RDI-L Insertion
&
+
DATA SHEET
Conditions
+
&
/
K2 Byte Bits 6-8 are not modified
and automatic insertion of RDI-L in
Tx Line Data is disabled.
OW Frame Pulse at OW/APS Port
leads MSB of E1 and E2 Bytes by 1
bit.
disables Transport Layer Interrupts
disables Path Layer Interrupts
interrupts only on positive edges of
alarms
/
/
/
K2, 6 - 8 =
"110"
K2, 6 - 8 =
"000"
K2, 6 - 8 =
"110"
Bit Equal to "0"
& = Logical AND
+ = Logical OR
/ = Logical NOT
= = Control State
&
&
&
&
LEGEND
+
Tx Line
K2 Byte
Bits 6 - 8
effective only if
See Table 26.
See Table 27.
TXC-06101
Comments
Ed. 3, April 2001
OA = "1"
TXC-06101-MB
PHAST-1

Related parts for TXC-06101AILQ