TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 180

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Proprietary TranSwitch Corporation Information for use Solely by its Customers
PHAST-1
DATA SHEET
TXC-06101
A Receive Software Reset is initiated by RSWRES (CR3; 0FB[H], Bit 1). A Transmit Software Reset is Con-
trolled by TSWRES (CR15; 1DF[H], Bit 6). A Software Reset consists of resetting the Counters and Status Bits
associated with the Transmit or Receive Sides. A Chip Reset is initiated by CHPRES (CR18; 1DC[H], Bit 0). A
Chip Reset is similar to a Hardware Reset (pin RST), except that control registers and the µPro interface are
not affected. A Software Reset or Chip Reset is initiated by setting the appropriate control bit to "1". The reset
state will remain in effect until the control bit is returned to the "0" logic level. Note that RSWRES will disable
the Frame Pulse and clock of the Rx Ring Port. Ring Port Data will continue to be sent out but B3 errors may be
repeated.
MICROPROCESSOR INTERFACE
The µPro Interface is the means by which PHAST-1 is queried and controlled. Three microprocessor types are
supported: Intel, Motorola and Multiplexed Address/Data bus. The pins µPSEL0 and µPSEL1 determine the
interface type.
Software Operations
All Memory Locations are Read and Write except for: 000[H] - 004[H], Clear on Read Status Registers and
Unlatched Status Registers which are Read Only. Status or Control Register bit positions marked "Unused" are
not equipped. Bit 7 of CR6 (0FE[H]), and Bits 7 and 6 of CR19 (1DB[H]) are marked "Reserved". These bits
should be set to "0". Failure to do so may jeopardize software compatibility in future device revisions. The Con-
trol bit RAMTSTEN (CR6; 0FE[H], Bit 6) is provided to allow memory testing. When it is set to "1" RAM access
by all internal operations is inhibited. Two controls: TEST1 and TEST2 (CR17; 1DD[H], Bits 4 and 3) are used
for Internal TXC tests. These must be set to "0" for normal operation.
All Counters clear on Read. Writing to a 16-Bit Counter is accomplished by first writing the HIBYTE Location
(1FF[H]) then writing to the Lower Order Register. Reading is accomplished by reading the lower order register
then reading HIBYTE. Registers 0F6[H] and 1F6[H] are non-latching registers used for Receive Side and
Transmit Side counter overflows, respectively. One bit is provided for each counter except for the Pointer Incre-
ment and Decrement Counters. The Rx Pointer Increment and Decrement Counters use the same bit to indi-
cate overflow. Similarly, the Tx Pointer Increment and Decrement Counters are combined into a single bit.
There are no overflow indication bits for the Tx B1, B2 or B3 counters.
Alarm reporting is accomplished with seven sets of three Status Registers (SR0 - SR6), each of which is com-
posed of two latching locations and one non-latching location, and three single Status Registers (SR7 - SR9),
which provide only unlatched values. In either case, the alarm is indicated by the appropriate bit being set to
"1". In SR0 - SR6, each alarm occupies the same bit position in each of the three registers. The First Register
of the set provides latched values that clear (reset to "0") when the register is read. The Second Register con-
tains latched values that are cleared, on a per bit basis, by writing a "1" to the bit that is to be cleared (multiple
bit positions may be simultaneously cleared). It must be noted that the clearing of either latched register is
reflected in the contents of the other register. For example, reading the First Register clears all alarms in both
the First and Second Registers. Similarly, Writing a "1" to a bit in the Second Register clears that alarm bit in
both the First and Second Registers. For test purposes, writing a "1" to any bit(s) with the address of the Third
Register of SR0 - SR6 will set to "1" the corresponding bit(s) in the First and Second Registers. The Third Reg-
ister of the set and SR7 - SR9 contain unlatched values that provide a real time indication of the alarm status.
Bits in these locations will be at a logical "1" for the duration of the causative event.
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TXC-06101-MB
Ed. 3, April 2001