TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 93

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

STATUS REGISTER 5
See notes on next page
Address
1EC
1E8
1E9
[H]
Bit
7
6
5
4
3
2
1
0
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DRCOFA Datacom Reference Change of
TRCOFA Tx Reference Change of Frame
Symbol
TFIFOE
TCPTR
TBPE
LOTR
TTE1
TFE
Tx Bus Parity Error:
any parity error detected at Tx
Terminal Input
Tx Frame Error:
one or more A1 or A2 bits in error
at Tx Terminal Interface
Tx Concatenated Pointer:
TLOP declared and
Tx Terminal E1 Alarm:
5 or more bits Set to "1" in the E1
Byte at the Tx Terminal Port
Alignment: any TFRI pulse that
varies in frame position from the
previous pulse
Frame Alignment: any DFRI
pulse that varies in frame position
from the previous pulse
Loss of Tx Reference:
SPE-only or SONET Modes
Selected; TCLK = "1" and either;
200 - 2000 ns without transitions
at TLCI or TFRIEN = "1" and 8
frames without transitions on
TFRI
Datacom Mode selected;
RTLOOP = "0" or TTOHEN = "1"
and either; 200 - 2000 ns without
transitions at DRCI or DFRIEN =
"1" and 8 frames without transi-
tions on DFRI
Tx FIFO Error:
Transmit FIFO Overflow or
Underflow when Tx re-timing is
enabled as shown below
SPE-only Mode
Datacom Mode
C1J1EN
TXRTM
NDF Bits =
SS Bits
I Bits
D Bits
Enter
=
=
=
"1001"
"00"
"1"
"1"
0 0 0 1
0 0 1 -
0 1 -
1 -
- 93 of 196 -
1 -
DATA SHEET
Conditions
-
no parity error detected at Tx
Terminal Input
one pair of A1 and A2 bytes
received without errors at Tx
Terminal Interface
TLOP not declared
or concatenation indication
not received
fewer than 5 bits set to "1" in
the E1 Byte at the Tx Termi-
nal Port
No Exit Conditions - Latched
Values are reset by µPro
Read of 1E8[H] or Writing "1"
to this bit in 1E9[H].
No Exit Conditions - Latched
Values are reset by µPro
Read of 1E8[H] or Writing "1"
to this bit in 1E9[H].
any transitions on enabled
pins listed for Enter condi-
tions
No Exit Conditions - Latched
Values are reset by µPro
Read of 1E8[H] or Writing "1"
to this bit in 1E9[H].
Exit
notes 1, 2
1EC, see Note 3.
inhibited if TLOC or
TLOS is declared or
C1J1EN = "1"
inhibited if TLOC,
TLOS, TLOF or TAIS-L
is declared or if
C1J1EN = "1"
inhibited if TLOC, TLOS
or TLOF is declared or
TE2A = "0"
1EC, see Note 3.
Valid only in Datacom
Mode.
1EC, see Note 3.
inhibited when:
SPE-only
Datacom
C1J1EN
TXRTM
1EC, see Note 4.
Comments
TXC-06101
Ed. 3, April 2001
TXC-06101-MB
0
0
0
0
PHAST-1
0
1
-
0