TXC-06101AILQ Transwitch Corporation, TXC-06101AILQ Datasheet - Page 77

• Manufacturer Part Number: TXC-06101AILQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-06101AILQ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Address [H]
04A-04F
041-043
052-057
040
044
045
046
047
048
049
050
051
058
and
059
Proprietary TranSwitch Corporation Information for use Solely by its Customers
Status Bits
RLFEBEOF
RPMOVOF
RB1COF
RB2COF
RPJOF
Control Bits
CNT16EN
CNT16EN
CNT16EN
RSWRES
RSWRES
RSWRES
RSWRES
RSWRES
DISRLAL
DISRLAL
DISRLAL
FEBE-L Count: count of FEBE-L Errors that are incoming on the Rx Line.
This is an 8 or 16-Bit, Clear on Read, Saturating Counter. In 8-Bit Mode
the total counter value is available at this location. In 16-Bit Mode this
location is the Lower Order 8 Bits. The Higher Order 8 Bits are readable in
Location 1FF[H]. The Lower Order Byte must be Read first in 16-Bit Mode.
Counting is inhibited upon declaration of RLOC, RLOS, RLOF, or RAIS-L
or by DISRLAL.
Internal Use - Do Not Access
Rx PJ Count: count of all Positive and Negative Pointer Justifications that
are incoming on the Rx Line. This is an 8-Bit, Clear on Read, Saturating
Counter. Counting is inhibited upon declaration of RLOC, RLOS, RLOF or
RAIS-L.
Rx Inc Count/Dec Count: two - 4-Bit Counters. Bits 7-4 accumulate
Pointer Increments incoming on the Rx Line. Bits 3-0 accumulate Pointer
Decrements incoming on the Rx Line. The Pointer Increment/Decrement
counters are increased by one only when a match of eight or more of the
ten I-bits and D-bits to either the increment or decrement indication
occurs. Both Counters are Saturating and Clear on Read. Counting is
inhibited upon declaration of RLOC, RLOS, RLOF or RAIS-L.
Rx B1 Error Count: count of B1 Errors that are incoming on the Rx Line.
This is an 8 or 16-Bit, Clear on Read, Saturating Counter. In 8-Bit Mode
the total counter value is available at this location. In 16-Bit Mode this
location is the Lower Order 8 Bits. The Higher Order 8 Bits are readable in
Location 1FF[H]. The Lower Order Byte must be Read first in 16-Bit Mode.
Counting is inhibited upon declaration of RLOC, RLOS or RLOF or by
DISRLAL.
Rx B2 Error Count: count of B2 Errors that are incoming on the Rx Line.
This is an 8 or 16-Bit, Clear on Read, Saturating Counter. In 8-Bit Mode
the total counter value is available at this location. In 16-Bit Mode this
location is the Lower Order 8 Bits. The Higher Order 8 Bits are readable in
Location 1FF[H]. The Lower Order Byte must be Read first in 16-Bit Mode.
Counting is inhibited upon declaration of RLOC, RLOS, RLOF or RAIS-L
or by DISRLAL.
Internal Use - Do Not Access
Rx B1 Error Mask: the contents of this location are exclusive-OR gated,
bit by bit, with the B1 Byte output at the Rx Terminal Port.
Frm-1 (Z1, Z2, C1, F1, K1, K2): respective bytes received in the previous
frame where : 04A[H] = Frm-1 Z1 and 04F[H] = Frm-1 K2.
Internal Use - Do Not Access
Rx B2 Error Mask: the contents of this location are exclusive-OR gated,
bit by bit, with the B2 Byte output at the Rx Terminal Port.
Frm-2 (Z1, Z2, C1, F1, K1, K2): respective bytes received two frames ear-
lier where ; 052[H] = Frm-2 Z1 and 057[H] = Frm-2 K2.
Internal Use - Do Not Access
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DATA SHEET
Description
TXC-06101
Ed. 3, April 2001
TXC-06101-MB
PHAST-1