CY7C019V-25AC Cypress Semiconductor Corp, CY7C019V-25AC Datasheet - Page 12

• Manufacturer Part Number: CY7C019V-25AC
• Description: SRAM Chip Async Dual 3.3V 1.125M-Bit 128K x 9-Bit 25ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C019V-25AC

• Package: 100TQFP
• Timing Type: Asynchronous
• Density: 1.125 Mb
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 17 Bit
• Number Of I/o Lines: 9 Bit
• Number Of Ports: 2
• Number Of Words: 128K

Document #: 38-06044 Rev. *C
Switching Waveforms
Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
Busy Timing Diagram No. 1 (CE Arbitration)
CE
CE
Right Address Valid First:
Note:
37. If t
L
ADDRESS
ADDRESS
R
Valid First:
ADDRESS
ADDRESS
Valid First:
ADDRESS
ADDRESS
PS
is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
BUSY
BUSY
BUSY
BUSY
CE
CE
CE
CE
L,R
L,R
R
R
L
R
L
R
L
L
R
R
L
L
(continued)
t
t
PS
PS
ADDRESS MATCH
ADDRESS MATCH
t
t
RC
RC
or t
or t
t
t
PS
PS
WC
WC
t
t
[37]
BLA
BLA
ADDRESS MATCH
ADDRESS MATCH
[37]
t
t
BLC
BLC
ADDRESS MISMATCH
ADDRESS MISMATCH
t
t
BHA
BHA
t
t
BHC
BHC
CY7C008V/009V
CY7C018V/019V
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