CY7C019V-25AC Cypress Semiconductor Corp, CY7C019V-25AC Datasheet - Page 9

• Manufacturer Part Number: CY7C019V-25AC
• Description: SRAM Chip Async Dual 3.3V 1.125M-Bit 128K x 9-Bit 25ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C019V-25AC

• Package: 100TQFP
• Timing Type: Asynchronous
• Density: 1.125 Mb
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 17 Bit
• Number Of I/o Lines: 9 Bit
• Number Of Ports: 2
• Number Of Words: 128K

Document #: 38-06044 Rev. *C
Switching Waveforms
Write Cycle No. 2: CE Controlled Timing
Write Cycle No. 1: R/W Controlled Timing
Notes:
24. R/W must be HIGH during all address transitions.
25. A write occurs during the overlap (t
26. t
27. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
28. To access RAM, CE = V
29. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
30. During this period, the I/O pins are in the output state, and input signals must not be applied.
31. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
CE
DATA OUT
ADDRESS
ADDRESS
CE
DATA IN
DATA IN
to be placed on the bus for the required t
as short as the specified t
HA
[28]
[28]
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
R/W
R/W
OE
IL
PWE
, SEM = V
.
t
t
(continued)
SA
SA
NOTE 30
SCE
IH
.
or t
SD
PWE
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
) of a LOW CE or SEM.
t
[24, 25, 26, 31]
HZWE
[24, 25, 26, 27]
[29]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[27]
t
t
SD
SD
PWE
or (t
HZWE
t
t
HA
HA
t
t
+ t
HD
HD
SD
t
LZWE
) to allow the I/O drivers to turn off and data
CY7C008V/009V
CY7C018V/019V
t
HZOE
[29]
NOTE 30
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