CY7C019V-25AC Cypress Semiconductor Corp, CY7C019V-25AC Datasheet - Page 7

• Manufacturer Part Number: CY7C019V-25AC
• Description: SRAM Chip Async Dual 3.3V 1.125M-Bit 128K x 9-Bit 25ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C019V-25AC

• Package: 100TQFP
• Timing Type: Asynchronous
• Density: 1.125 Mb
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 17 Bit
• Number Of I/o Lines: 9 Bit
• Number Of Ports: 2
• Number Of Words: 128K

Document #: 38-06044 Rev. *C
Switching Characteristics
Data Retention Mode
The CY7C008V/009V and CY7018V/019V are designed with
battery backup in mind. Data retention voltage and supply
current are guaranteed over temperature. The following rules
ensure data retention:
Notes:
17. t
18. CE = V
t
t
t
t
t
t
t
t
1. Chip enable (CE) must be held HIGH during data retention,
2. CE must be kept between V
3. The RAM can begin operation >t
WH
BDD
INS
INR
SOP
SWRD
SPS
SAA
INTERRUPT TIMING
SEMAPHORE TIMING
within V
during the power-up and power-down transitions.
minimum operating voltage (3.0 volts).
Parameter
BDD
[17]
is a calculated parameter and is the greater of t
CC
, V
CC
in
to V
= GND to V
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
INT Set Time
INT Reset Time
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
CC
– 0.2V.
[16]
CC
, T
A
= 25°C. This parameter is guaranteed but not tested.
CC
Description
– 0.2V and 70% of V
Over the Operating Range
RC
after V
WDD
CC
–t
PWE
reaches the
(actual) or t
CC
[10]
DDD
Min.
–t
13
10
(continued)
5
5
SD
Timing
V
CE
ICC
CC
(actual).
-15
Parameter
DR1
Max.
15
15
15
15
CY7C008V/009V
CY7C018V/019V
Min.
15
10
5
5
3.0V
@ VCC
Data Retention Mode
Test Conditions
V
-20
CC
V
Max.
to V
CC
20
20
20
20
DR
> 2.0V
CC
= 2V
– 0.2V
CY7C008V/009V
CY7C018V/019V
Min.
17
12
5
5
[18]
3.0V
-25
Max.
Max.
25
20
20
25
50
Page 7 of 18
V
t
IH
RC
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µA