ISL5216KI-1 Intersil, ISL5216KI-1 Datasheet - Page 10

• Manufacturer Part Number: ISL5216KI-1
• Description: Digital Down Converter 196-Pin BGA
• Manufacturer: Intersil

Specifications of ISL5216KI-1

• Package: 196BGA
• Operating Temperature: -40 to 85 °C

NOTE:
NOTE:
Level Detector
An input level detector is provided to monitor the signal level
on any of the input busses. The input bus, input format, and
the level detection type are programmable (see
Microprocessor Interface , GWA registers F804h, F805h and
F806h). This signal level represents the wideband signal from
the A/D and is useful for controlling gain/attenuation blocks
ahead of the converter.
The supported monitoring modes include integrated
magnitude (like the HSP50214 w/o the threshold) and leaky
integration (Y
or 2
be programmed from 2 to 65537 samples (or continuous for
the leaky integrator case). The output is 32 bits and is read via
the μP interface.
Note that the accumulators in the input level detector are 32
bits wide. This may limit the integration range to as few as
512 samples (for a 42dB exponent range).
12. To select this mode, set IWA *000H/GWA F804H bits 17, 16, 8 and 7 to 1, 1, 0 and 0 respectively.
13. To select this mode, set IWA *000H/GWA F804H bits 17, 16, 8 and 7 to 1, 1, 0 and 1 respectively.
011
X(-1) = 0
X(-1) = 1
000
001
010
EXPONENT
EXPONENT
-16
ABSOLUTE
16
(see GWA = F805h). The measurement interval can
VALUE
MSB
15-BIT MODE: 15-BIT MANTISSA (15:1), 2-BIT EXPONENT (-1, 0), 18dB MAXIMUM EXPONENT RANGE (Note 12)
n
16-BIT MODE: 16-BIT MANTISSA (15:0), 1-BIT EXPONENT (-1), 6dB MAXIMUM EXPONENT RANGE (Note 13)
= X
FIGURE 1. INTEGRATED MODE
0
6
12
18
0
6
n
GAIN (dB)
GAIN (dB)
x A + Y
n-1
10
x (1-A)) where A = 1, 2
2
0, -8, -12, -16
X15
X15
X15
X15
X15
X15
X14
X14
X14
X14
X14
X14
X13
X13
X13
X13
X13
X13
32
-8
, 2
X12
X12
X12
X12
X12
X12
-12
PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING
PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING
ISL5216
,
X11
X11
X11
X11
X11
X11
X10
X10
X10
X10
X10
X10
2
0, -8, -12, -16
FIGURE 2. PEAK DETECTOR (See “Errata” on page 63)
16
X9
X9
X9
X9
X9
X9
X
A =
2
16
0, -8, -12, -16
EN
X8
X8
X8
X8
X8
X8
FIGURE 3. LEAKY INTEGRATOR
A
X7
X7
X7
X7
X7
X7
B
Σ
X6
X6
X6
X6
X6
X6
A > B
X5
X5
X5
X5
X5
X5
Σ
Y
X4
X4
X4
X4
X4
X4
N
R
G
E
= A * X + (1 - A) * Y
R
E
G
EN
X3
X3
X3
X3
X3
X3
32
32
X2
X2
X2
X2
X2
X2
Y
July 13, 2007
X1
X1
X1
X1
X1
X1
N-1
FN6013.3
X0
X0
0
0
0
0