ISL5216 Intersil Corporation, ISL5216 Datasheet
ISL5216
Available stocks
Related parts for ISL5216
ISL5216 Summary of contents
Page 1
... NCO, digital filters, a resampling filter, a Cartesian-to-polar coordinate converter and an AGC loop. The ISL5216 accepts four channels of 16-bit fixed 14-bit mantissa / 3-bit exponent floating point real or complex digitized IF samples which are mixed with local quadrature sinusoids. Each channel carrier NCO frequency is set independently by the microprocessor. The output of the mixers are fi ...
Page 2
... D(15:-1) ENID INPUT SELECT, FORMAT, DEMUX CLK RESET SYNCI SYNCO SYNCI0 SYNCI1 P(15:0) SYNCI2 SYNCI3 TRST TCLK TMS TDI TDO 2 ISL5216 LEVEL DETECTOR I NCO / MIXER / CIC Q CHANNEL 0 I NCO / MIXER / CIC Q CHANNEL 1 BUS ROUTING I NCO / MIXER / CIC Q CHANNEL 2 I NCO / MIXER / CIC Q CHANNEL 3 µ ...
Page 3
... B3 B2 ENIB C12 N C15 C14 C10 P C13 C11 C9 POWER PIN GROUND PIN VCC1 = +2.5V CORE SUPPLY VOLTAGE VCC2 = +3.3V I/O SUPPLY VOLTAGE 3 ISL5216 196 LEAD BGA TOP VIEW A11 A13 A15 SD1A SYNCA SYNCB A10 VCC1 GND VCC1 GND VCC2 ENIA ...
Page 4
... SYNCI I Global synchronization input signal. Used to align the processing with an external event or with other ISL5216 or HSP50216 devices. SYNCI can update the carrier NCO, reset decimation counters, restart the filter compute engine, and restart the output section among other functions. For most of the functional blocks, the response to SYNCI is programmable and can be enabled or disabled ...
Page 5
... SYNCO O Synchronization Output Signal. The processing of multiple ISL5216 or HSP50216 devices can be synchronized by tying the SYNCO from one ISL5216 device (the master) to the SYNCI of all the ISL5216 / HSP50216 devices (the master and slaves). RESET I Reset Signal. Active low. Asserting reset will halt all processing and set certain registers to default values. ...
Page 6
... The output data can also be read th via the microprocessor interface for all channels that are order, or 65536 for synchronized. The ISL5216 is specified to operate to a maximum clock rate of 95MSPS over the industrial temperature range (-40 voltage range is 3.3V ± 0.165V while the core power supply voltage is 2.5V ± ...
Page 7
... This mode inserts zeros between the data samples, interpolating the input data stream up to the clock rate. On reset, the part is set to gated mode and the input enables are disabled. The 7 ISL5216 EXTERNAL/TEST SELECT (IWA *000 - 15 or GWA F804 - 15) ...
Page 8
... HSP50216 and their functionality remains unchanged. The 14-bit mantissa / 2-bit exponent mode present in the HSP50216 has been extended from a 12dB range to 18dB in the ISL5216. This Floating Point Input Mode Bit Mapping Tables (( 11-BIT MODE 13-BIT MANTISSA (15:3), 3-BIT EXPONENT (2:0), 30dB EXPONENT RANGE (Note 3) ...
Page 9
... X15 NOTES: 10. For compatibility with legacy HSP50216 11, 12 and 13 bit floating point modes as well as the new ISL5216 modes, the most significant exponent bit is taken as X2 OR’d with X-1. Either input may be used for the MSB of the exponent when the other is tied low. ...
Page 10
... Note that the accumulators in the input level detector are 32 bits wide. This may limit the integration range to as few as 512 samples (for a 42dB exponent range). ABSOLUTE VALUE MSB 16 0, -8, -12, -16 2 FIGURE 1. INTEGRATED MODE 10 ISL5216 PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING X14 X13 X12 X11 X10 X9 X14 X13 X12 ...
Page 11
... Number of delays (1 for the ISL5216 Number of stages /R, making the CIC output order CIC and f is the maximum clock frequency available on max through fifth stages, respectively, while the comb bit -1 ...
Page 12
... Shift Factor = 45 - Ceiling(log CIC barrel shifts of greater than 45 will cause MSB bits to be lost. Most of the floating point modes on the ISL5216 make use of the CIC barrel shifter for gain. This limits the maximum usable decimation. In particular, shift factor minus -45 ...
Page 13
... AM and FM filtering. There are seven outputs from each back end processing section. These are I and Q directly out of the filter compute engine (I2, Q2), I and 13 ISL5216 AGC LOOP FILTER PATH 0 (4:0) ...
Page 14
... CIC filter output (which can also be another backend section), the output of the filter compute engine (fed back to the input) or the magnitude and dφ/dt fed back from the cartesian-to-polar coordinate converter. 14 ISL5216 DOWN SHIFT PLACES 1..-25 WITH RND ...
Page 15
... For program flow, a wait for input sample(s) instruction, a loop counter load, and several jumps (conditional and unconditional) are provided. The ISL5216 evaluation board includes software for automatically generating FIR control programs for most filter requirements. Examples of programs FIR control programs are given below. ...
Page 16
... Illustrating this concept with Filter Example #3, a higher speed filter chain might be comprised of one 19 tap decimate-by-2 halfband filter followed tap shaping FIR filter with no decimation. The program for this example could be: 16 ISL5216 SAMPLE FILTER #3 PROGRAM STEP 0 Wait for enough input samples (2 in this case) 1 ...
Page 17
... This assures that the gains of the four back end sections are the same. The gain error, however, is only computed from every fourth output sample. The back end processing sections of two or more ISL5216s can be combined using the same polyphase approach, but the AGC gain from one part cannot be shared with another part (except via the µ ...
Page 18
... RESET SEQUENCER SYNC THRESHOLD DECREMENT 1 WAIT COUNTER DECREMENT 2 LOOP LOOP COUNTER COUNTER PRELOAD RESAMPLER NCO 18 ISL5216 FIR# - WRITE DESTINATION FIR# - COMPUTE READ ALIAS POINTER MASK DATA ADDRESS STEP SIZE COMPUTE TO COMPUTE FIR TYPE NUMBER OF OUTPUTS TAPS/OUTPUT COMPUTE READS/TAP COUNTERS INSTR/TAP RAM ADDR BLOCK START ...
Page 19
... U/C FIR is a normal FIR with the U/C bit enabled. 17. Other codes may be added in the future. 17:15 Steps per FIR Specifies the number of steps per FIR instruction sequence (load with value minus 1) (set to 0 for all FIR types except complex which is set to 1). 19 ISL5216 INSTRUCTION BIT FIELDS ...
Page 20
... Data Memory 0-255, usually equal to the decimation factor for the FIR in this instruction. Block-to-Block Step 62:53 Coefficient Memory Memory base address of coefficients, 0-1023, 0-511 are valid on the ISL5216. Block Start 20 ISL5216 INSTRUCTION BIT FIELDS (Continued) DESCRIPTION ...
Page 21
... B data is not used for asymmetric, resampling, and complex filters). 122:120 Coefficient Memory (ADDRC) Usually set to 1. 122:120 Step Size ISL5216 INSTRUCTION BIT FIELDS (Continued) DESCRIPTION Memory Block Size 128 256 512 1024 Value (taps/2) or floor((taps+1)/2). (taps+1)/2 or floor((taps+1)/2). ...
Page 22
... T - number of taps minus clocks/calculation (=floor((taps+1)/2) for symmetric, = taps for asymmetric) The rest of the instruction RAM would typically be filled with NOP instructions: 0000 0000 0000 0000 0000 0000 0000 0000 22 ISL5216 INSTRUCTION BIT FIELDS (Continued) Step size 8:0 = 1JJJJJ100b example: jump RSCO, step 0 = 0000,0000,0000,0104h 5 ...
Page 23
... NCO center frequency update strobe location (IWA register *009h SYNCI (if enabled not possible to represent some frequencies 23 ISL5216 exactly with an NCO and therefore, phase error accumulates eventually causing a bit slip, the phase accumulator length has been sized to where the error is insignificant ...
Page 24
... AGC MULTIPLIER/SHIFTER † Controlled via microprocessor interface. 24 ISL5216 sampled when new data enters the multiplier / shifter. The limit detector detects overflow in the shifter or the multiplier and saturates the output of I and Q data paths independently. The shifter has a gain from 0 to 90.31dB in 6 ...
Page 25
... LG to 15, and 4-bit binary exponent value ranging from 15. The composite (shifter and multiplier) AGC scaling 25 ISL5216 Gain range is from 0.0000 to 2.329(0.9375)2 2.18344. The scaled gain error can range (depending (X)2 ]) threshold) from 0 to 2.18344, which maps to a “ ...
Page 26
... IWA register *013h selecting loop gain and the settling mode. In the ISL5216, a SYNCI signal will clear the AGC loop filter accumulator if GWA register F802h bit 27 is set. This sets the AGC to unity gain or to the lower gain limit (IWA *011h bits 15: larger than unity ...
Page 27
... ISL5216 The magnitude and phase computation requires 17 clocks for full precision. At the end of the 17 clocks, the magnitude and phase are latched into a register to be held for the next stage, either the output formatter or frequency discriminator. o PHASE ( ...
Page 28
... To configure more than one channel's output onto a serial data output, the SD1 serial outputs and syncs from each channel (0,1, 2 and 3) are brought to each of the SD1 serial output sections and the SD2 serial outputs are brought to 28 ISL5216 OUTPUT SECTION FIXED TO M ...
Page 29
... P(15:0), three address pins, ADD(2:0), a write strobe (WR), a read strobe (RD) and a chip enable (CE). Indirect addressing is used for control and configuration of the ISL5216. The control and configuration data to be loaded is first written to a 32-bit holding register at direct (external) addresses ADD(2: and 1, 16 bits at a time ...
Page 30
... RAM and instruction bit fields can be written to or read from.) The ISL5216 output data from the four channels is available through the microprocessor interface as well as from the serial data outputs. A FIFO-like interface is used to read the output data through the microprocessor interface ...
Page 31
... SYNCO and internal SYNCI by writing to GWA F80AH. A write to F809H will also work if the SYNCO pin is externally connected to the SYNCI pin. Recommended ISL5216 Channel Reconfiguration Procedure: 1. Disable the serial output for the desired channel in register GWA F801H - bits 3:0. ...
Page 32
... ISL5216 Filter Compute Engine Data RAM Test The ISL5216 provides read / write access to the data RAM used by a channel’s filter compute engine. To access the data RAM for testing, set bit 15 of GWA F800H. Data must be written to the RAM pairs - 24 bit Q first, then 24 bit I ...
Page 33
... RESET (Note: This bit is inverted with respect to the RESET input pin). 10 ENIA. 9 ENIB. 8 ENIC. 7 ENID. 6 SYNCI. Mask revision number. ISL5216 devices return 3 or higher (0, 1 and 2 were used for HSP50216). Level detector integration done. Active high. New FIFO output data available (used for polling mode vs interrupt mode) Active low. ...
Page 34
... CIC shift code. Set to 111 to disable. 17 Enables the new (ISL5216) floating point modes -- the 11, 12, 13 and 14-bit modes with gain, and 15 and 16-bit modes with 18 dB and 6 dB ranges, respectively. The X-1 input must be used for 14, 15 and 16-bit modes. See Floating Point Input Mode Bit Mapping Tables for details ...
Page 35
... FDM channel by channel basis. It does, however, reduce the overall dynamic range. An alternate way is to add attenuation at the RF and adjust the whole range upward. This does not reduce the overall range but only shift it, with the shift being done on all channels simultaneously. 35 ISL5216 FUNCTION MANTISSA / EXP EXPONENT RANGE (dB) ...
Page 36
... The value in the active register can be read at this address (the center frequency control before the serially loaded offset value is added). To read the value, either write this address to A(1: and then read at A(1: and 01, or read the value at A(1: and 01 after writing to this address and before writing a new address to either A(1: 11. 36 ISL5216 FUNCTION FUNCTION Set to zero. ...
Page 37
... This forces the NCO to a known phase so the phase of multiple channels can be aligned. 15 Force NCO load. This bit, when set, zeroes the feedback in the resampler NCO phase accumulator. This is provided for test or to use the resampler for phase instead of frequency shifting. 37 ISL5216 FUNCTION FUNCTION FUNCTION FUNCTION FUNCTION ...
Page 38
... This location loads the AGC accumulator. If the loop attack/decay gain is set to zero and this value is within the AGC gain limits, the AGC will hold this value. If not, the AGC will be set to this gain ( limit) and then start to settle. format is four exponent bits (15:12), and 12 mantissa bits, (11:0). 38 ISL5216 FUNCTION FUNCTION FUNCTION FUNCTION Set to zero ...
Page 39
... PSK modulation. The resulting phase is 18 bits. 2:0 DiscDelay(2:0). Sets the delay, in sample times, for the dφ/dt calculation. 000 1 111 8 39 ISL5216 FUNCTION FUNCTION TABLE 22. AGC GAIN LIMITS REGISTER (IWA = *011h) FUNCTION TABLE 23. AGC THRESHOLD REGISTER (IWA = *012h) FUNCTION FUNCTION ...
Page 40
... Enables the serial output for this channel to pin SD2D. 11:0 Output hold-off delay. This parameter adds additional delay from the output of the filter compute engine to start of the serial output stream for multiplexing channels. Load with the desired delay (0 = zero one two, etc.). 40 ISL5216 FUNCTION dBFS + -89 +1 ...
Page 41
... Seventh serial slot in Serial Data Output 1 (SD1x See bits 7:0 of Table 26 for functional description of bits 23:16. 15:8 Sixth serial slot in Serial Data Output 1 (SD1x See bits 7:0 of Table 26 for functional description of bits 15:8. 7:0 Fifth serial slot in Serial Data Output 1 (SD1x See bits 7:0 of Table 26 for functional description of bits 7:0. 41 ISL5216 FUNCTION FUNCTION ...
Page 42
... For the HSP50216 backward compatibility, the original 3-bit phase offset (IWA *004 bits 8:6) is added to the new 16-bit phase offset register. HSP50216 configurations use IWA *004. New configurations should set *004 bits 8:6 to zero and use this register. This register is set the reset pin. 42 ISL5216 FUNCTION FUNCTION FUNCTION ...
Page 43
... See the Filter Compute Engine and Filter Sequencer sections of the data sheet for more details. Tables of Global Write Address (GWA) Registers NOTE: These Global Write Addresses control global functions on the ISL5216, so they are not repeated for each channel. The top five address bits select this set of registers (F8XXh). ...
Page 44
... When this bit is set, the CIC decimation counter is reset on SYNCI. 24 When this bit is set, the serial output block is reset on SYNCI. If bit 4 in location GWA F803h is set, the serial clock divider is also reset. 23:16 Same functions as 31:24 for channel 1. 15:8 Same functions as 31:24 for channel 2. 7:0 Same functions as 31:24 for channel 3. 44 ISL5216 FUNCTION FUNCTION ...
Page 45
... Set to 000 for fixed point inputs. 17 Enables the new (ISL5216) floating point modes; the 11-, 12-, 13- and 14-bit modes with 42dB of gain, and 15- and 16-bit modes with 18dB and 6dB ranges, respectively. The X-1 input must be used for 14-, 15- and 16-bit modes. See Floating Point Input Mode Bit Mapping Tables for details ...
Page 46
... The ENI signal for this input is either bit 11 in the channel register at IWA *000h or the strobe generated by a write to location GWA F808h (selected via bit 12 of the channel register at IWA *000h). 46 ISL5216 FUNCTION FUNCTION + (1-A)*Y , where A is the gain selected in bits 19:18) ...
Page 47
... Channel Input Select / Format *001h 15:0 PN Gain *002h 15:0 CIC Decimation 47 ISL5216 FUNCTION TABLE 46. SYNCO STROBE REGISTER (GWA = F809h) FUNCTION TABLE 47. SYNCI STROBE REGISTER (GWA = F80Ah) TABLE 48. TEST CRC REGISTER (GWA = F80Bh) FUNCTION The upper 16 bits of the I data path via the FIFO/AGC. The lower 8 bits of the I data path. ...
Page 48
... Serial Clock Control F804h 20:0 Input Level Detector Source Select F805h 21:0 Input Level Detector Configuration F806h 31:0 Input Level Detector result (valid when bit 1 of status word is set) F807h 15:0 µP / Test Input Bus F80Bh 31:0 BIST F820h - F83Fh 4:0 µP FIFO Read Order Control 48 ISL5216 FUNCTION ...
Page 49
... C, controlled via design or process parameters and not directly tested. Characterized upon initial design and at major A process or design changes. 49 ISL5216 Thermal Information Thermal Resistance (Typical) 196 Lead BGA Package (0.8 mm pitch +0.5V w/200 LFM Air Flow . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 50
... A(1:0) to P(15:0) Data Valid Time DSTRB Low to P(15:0) Valid DSTRB Disable Time (Note 25 P(15:0) Data Valid Time CE Hold Time from Rising Edge of DSTRB (only applies when ADD(1: R/W Setup Time to Falling Edge of DSTRB 50 ISL5216 = Core Supply: 2.5V ± 0.125V I/O Supply: 3.3 ± 0.165V , CC2 ...
Page 51
... NOTES: 24. The ISL5216 goes into reset immediately on RESET going low and comes out of reset on the 4th rising edge of CLK after RESET goes high. 25. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes. ...
Page 52
... Waveforms (Continued) CLK ADD(1:0) P(15:0) FIGURE 7. MICROPROCESSOR WRITE TIMING (µP MODE = ADD(1:0) P(15:0) FIGURE 8. MICROPROCESSOR READ TIMING (µP MODE = 0) 52 ISL5216 PSW PHW t t ASW AHW CHW t CSW t RCY AHR t CSF t CHR ...
Page 53
... Waveforms (Continued) CLK CE RD/WR ADD(1:0) P(15:0) DSTRB FIGURE 9. MICROPROCESSOR WRITE TIMING (µP MODE = 1) CE RD/WR ADD(1:0) P(15:0) DSTRB FIGURE 10. MICROPROCESSOR READ TIMING (µP MODE = 1) 53 ISL5216 R/WSF t PSR t CSR t ASR CSF t R/WSF t DSTH t PHR t AHR t CHR t R/WHR AHR t CHR t R/WHR ...
Page 54
... Waveforms (Continued) CLK SCLK (/2 THRU /16) SYNC SDXX 54 ISL5216 SCLK (DIVIDE PDL t SKEW2 t SKEW1 t PD FIGURE 11. SERIAL OUTPUT TIMING 2.0V 0. FIGURE 12. OUTPUT RISE AND FALL TIMES t PDL ...
Page 55
... FIGURE 15. 5TH ORDER ( CIC RESPONSE (R = DECIMATION FACTOR, f OUTPUT RATE) -100 -110 -120 NOTE: HBF4 not included in the ROMd Fir Filter Coefficient memory. See Note 26 of Table 52. FIGURE 17. ROMd HALFBAND FILTER ALIAS FREQUENCY RESPONSE 55 ISL5216 -20 - -60 - -100 -120 -140 0 ...
Page 56
... FREQUENCY (RELATIVE TO f NOTE: There is a 65dB limitation in SNR using the Re-Sampler Filter. FIGURE 18. POLYPHASE RESAMPLER FILTER BROADBAND FREQUENCY RESPONSE FIGURE 20. POLYPHASE RESAMPLER FILTER EXPANDED RESOLUTION PASSBAND FREQUENCY RESPONSE 56 ISL5216 (Continued -10 -20 -30 -40 -50 -60 -70 ...
Page 57
... ISL5216 TABLE 51. CIC PASSBAND AND ALIAS LEVELS 4TH ORDER 3RD ORDER PASSBAND ALIAS PASSBAND 0 <-200 0 -0.006 -159.651 -0.004 -119.738 -0.023 -135.233 -0.017 -101.425 -0.051 -120.818 -0.039 -90 ...
Page 58
... ISL5216 4TH ORDER 3RD ORDER PASSBAND ALIAS PASSBAND -6.063 -32.249 -4.547 -24.187 -6.463 -31.066 -4.847 -23.299 -6.877 -29.921 -5.158 -22.440 -7.306 -28.812 -5.480 -21.609 -7.750 -27.739 -5 ...
Page 59
... Halfband #4). These bits occupy the upper six bytes (24 bits) with the two LSBs of the lower byte (bits 9:8 of 31:0) being zero. The decimal value for the hexadecimal coefficient is calculated by first converting the hexadecimal value to decimal and the dividing ISL5216 DECIMATING DECIMATING HALFBAND #2 ...
Page 60
... The 22-bit ROMd FIR filter coefficients are located in the upper 22 bits of the Read register when read back from ROM memory. These bits occupy the upper three bytes (24 bits) with the two LSBs of the lower byte (bits 9:8 of 31:0) being zero. The decimal value for the hexadecimal coefficient is calculated by first converting the hexadecimal value to decimal and the dividing ISL5216 DECIMAL -0.002620220 FFE944 ...
Page 61
... LSBs of the lower byte (bits 9:8 of 31:0) being zero. The decimal value for the hexadecimal coefficient is calculated by first converting the hexadecimal value to decimal and the dividing ISL5216 TABLE 54. RESAMPLER FIR FILTER COEFFICIENTS COEFF ...
Page 62
... In addition to the newly-assigned pins, some of the 3.3V VCC lines of the HSP50216 have been changed to 2.5V on the ISL5216. The ISL5216 now has VCC1 (2.5V core supply pins) and VCC2 (3.3V for I/O pads). See pin descriptions for additional information. ...
Page 63
... All new control bits are inactive if set to zero for backward compatibility with HSP50216 software. Power-up Sequencing The ISL5216 core and I/O blocks are isolated by structures which may become forward biased if the supply voltages are not at specified levels. During the power-up and power-down operations, differences in the starting point and ramp rates of the two supplies may cause current to fl ...
Page 64
... M D1 0.003 BOTTOM VIEW SIDE VIEW V196.15x15 package information available on Intersil’s website ISL5216 A V196.12x12 196 BALL PLASTIC BALL GRID ARRAY PACKAGE SYMBOL D/E D1/ MD/ME bbb A1 aaa CORNER ...
Page 65
... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 65 ISL5216 A V196.15x15 196 BALL PLASTIC BALL GRID ARRAY PACKAGE ...