ISL5216KI-1 Intersil, ISL5216KI-1 Datasheet - Page 7

• Manufacturer Part Number: ISL5216KI-1
• Description: Digital Down Converter 196-Pin BGA
• Manufacturer: Intersil

Specifications of ISL5216KI-1

• Package: 196BGA
• Operating Temperature: -40 to 85 °C

(INVERTED AT THE I/O PAD)
(GWA F807 - 15:0)
or GWA F804 - 11)
Input Select/Format Block
Each front end block and the level detector block contains an
input select/format block. A functional block diagram is
provided in the above figure. The input source can be any of
the four parallel input busses (see Microprocessor Interface
Section Table 1, IWA *000h) or a test register loaded via the
processor bus (see Microprocessor Interface Section, GWA
register F807h).
The input to the part can operate in a gated or interpolated
mode. Each input data bus has an input enable (ENIx, x = A,
B, C or D). In the gated mode, one input sample is
processed per clock that the ENIx signal is asserted (low).
Processing is disabled when ENIx is high. The ENIx signal is
pipelined through the part to minimize delay (latency). In the
interpolated mode, the input is zeroed when the ENIx signal
is high, but processing inside the part continues. This mode
inserts zeros between the data samples, interpolating the
input data stream up to the clock rate. On reset, the part is
set to gated mode and the input enables are disabled. The
TESTENSTRB
GWA F804 - 14:13)
(IWA *000 - 11
EXTERNAL DATA
(IWA *000 - 14:13
(GWA F808)
NOTE: ENI* SIGNALS
TESTENBIT
REGISTER
INPUT SELECT
ARE ACTIVE HIGH
μP TEST
A(15:-1)
B(15:-1)
C(15:-1)
D(15:-1)
ENIA
ENIB
ENIC
ENID
or
or GWA F804 - 12)
(IWA *000 - 12
TEST ENI
SELECT
FREQUENCY (COF)
CARRIER OFFSET
7
TESTEN
15:0
15:0
ENI
COF SYNC
or GWA F804 - 15)
EXTERNAL/TEST
(IWA *000 - 15
SELECT
(1WA *000 - 2)
ENABLE
INPUT ENABLE HOLD OFF
COF
(ENABLED BY SYNCI)
15:0
EN
TWO’s COMPLEMENT
(GWA F802 - 30)
or GWA F804 - 10)
OFFSET BINARY
(IWA *000 - 10
FORMAT
(IWA *000 - 0)
OR
ENABLE PN
ISL5216
COF TO
CARRIER
NCO/MIXER
COF SYNC TO
CARRIER
NCO/MIXER
PN
GWA F804 - 17:16, 8:7)
14/2, 14/3, 15/2, 16/1
FLOATING POINT
inputs are enabled by the first global SYNCI signal or
SYNCIx signal, where X = 0, 1, 2 or 3.
The input section can select one channel from a multiplexed
data stream of up to eight channels. The input enable is
delayed by zero to seven clock cycles to enable a selection
register. The register following the selection register is
enabled by the non-delayed input enable to realign the
processing of the channels. The one-clock-wide input enable
must align with the data for the first channel. The desired
channel is then selected by programming the delay. A delay
of zero selects the first channel, a delay of one selects the
second, etc.
The parallel input busses are 17 bits wide allowing for up to 16
bits of fixed-point data or 14 bits of mantissa with three bits of
exponent for floating-point data. The input format may be twos
complement or offset binary format in either fixed or floating
11/3, 12/3, 13/3
FIXED POINT
(IWA *000 or
or GWA F8O4 - 6:4)
PROGRAMMABLE
DE-MULTIPLEX
CONTROL (0-7)
(IWA *000 - 6:4
TO
OFFSET FREQUENCY
DELAY
PN TO
CARRIER
NCO/MIXER
RESAMPLER
SOF SYNC
FLOATING POINT
or GWA F804 - 9)
(SOF)
FIXED POINT
(IWA *000 - 9
OR
(IWA *000 - 1)
INTERPOLATED/GATED
ENABLE
SOF
or GWA F804 - 3)
R
E
G
(IWA *000 - 3
MODE
15:0
SOF TO
RESAMPLER
NCO
SOF SYNC TO
RESAMPLER
NCO
DATA
TO
NCO/MIXER
OR
LEVEL
DETECTOR
July 13, 2007
DATA
SAMPLE
ENABLE
FN6013.3