ISL5216KI-1 Intersil, ISL5216KI-1 Datasheet - Page 31

• Manufacturer Part Number: ISL5216KI-1
• Description: Digital Down Converter 196-Pin BGA
• Manufacturer: Intersil

Specifications of ISL5216KI-1

• Package: 196BGA
• Operating Temperature: -40 to 85 °C

μP Read/Write Procedures
To Write to the Internal Registers:
To Write to the Internal Instruction/Coefficient RAMs:
To Read Internal Registers:
To Read Data Outputs:
To Read Instruction/Coefficient Values:
1. Load the indirect write holding registers at direct address
2. Write the Indirect Write Address of the internal register
3. Wait four clock cycles before performing the next write to
1. Put the filter compute engine of the desired channel into
2. Load the indirect write holding registers at direct address
3. Write the Indirect Write Address of the internal RAM
4. Wait four clock cycles before performing the next write to
5. After all data has been loaded, set the μPHold bit back
1. Write the Indirect Read Address of the internal register
2. Perform a read of the Indirect Read Holding Registers at
1. Set up the μP FIFO Read Order Control Register (located
2. Wait for interrupt or check flag.
3. Data can then be read, 16 bits at a time, at direct
4. Repeat step 3 for desired number of words.
5. Go to step 2.
1. Put the filter compute engine of the desired channel into
ADD(2:0) = 0 and 1 with the data for the internal register
(16 or 32 bits depending on the internal register being
addressed).
being addressed to direct address ADD(2:0) = 2 (Note: A
write strobe to transfer the contents of the Indirect Write
Holding Register into the Target Register specified by the
Indirect Address will be generated internally).
the indirect write holding registers.
the hold mode by setting bit 31 of the Filter Compute
Engine/Resampler Control register located at IWA =
*00AH (Note: The * is equal to 0, 1, 2 or 3 depending on
the channel being addressed). By setting bit 31 all FIR
processing for the channel addressed will be stopped.
ADD(2:0) = 0 and 1 with the data for the internal RAM
location.
location being addressed to direct address ADD(2:0) = 2
(Note: A write strobe to transfer the contents of the
Indirect Write Holding Register into the RAM location
specified by the Indirect Address will be generated
internally).
the indirect write holding registers.
low.
being addressed to direct address ADD(2:0) = 3.
direct address ADD(2:0) = 0 and 1.
at Global Write Address (GWA) = F820H - F83FH).
address 2, ADD(2:0) = 2.
the hold mode by setting bit 31 of the Filter Compute
Engine/Resampler Control register located at
IWA = *00AH (Note: The * is equal to 0, 1, 2 or 3
depending on the channel being addressed).
31
ISL5216
Recommended ISL5216 configuration
procedure following a hardware reset (i.e.
RESETb is pulsed low):
Recommended ISL5216 Channel
Reconfiguration Procedure:
2. Write the Indirect Read Address (IRA) of the internal
3. Wait four clock cycles.
4. Read the data at direct address ADD(2:0) = 0 and 1.
5. After all the data has been read, set the μPHold bit back
1. Load Global Write Address registers GWA F800H - GWA
2. For each signal processing channel (0-3):
3. Generate a SYNCI to enable the input data or to
1. Disable the serial output for the desired channel in
2. Disable the interrupts from the channel in register GWA
3. Set the μPHold bit in register IWA *00AH bit 31 to give the
4. Load the new filter configuration.
5. Load any other channel registers.
6. Clear the μPHold bit in register IWA *00AH bit 31.
7. Do a software channel reset by writing to IWA *019H.
8. Enable the serial outputs (GWA F801H) and interrupts
9. Generate a SYNCI to enable the input data or to
RAM/ROM location being addressed to direct address
ADD(2:0) = 3.
low.
F808H and GWA F820H - GWA F83FH.
a. Set μPHold bit located at Indirect Write Address
b. Load Filter Compute Engine Instruction RAMS.
c. Load Filter Compute Engine Coefficient RAMS.
d. Load IWA registers *000H - *019H and *01CH. (Clear
e. Wait 32 clocks (CLK) for the reset to complete in the
register GWA F801H - bits 3:0.
F802H bits 31, 23, 15, and 7.
processor access to the Filter Compute Engine
Instruction RAMS and Coefficient RAMS.
(GWA F802H).
synchronize the processing to external events or
generate a SYNCO by writing to GWA F80AH or F809H
(if SYNCO pin is tied to SYNCI pin).
synchronize the processing to external events or
generate a SYNCO and internal SYNCI by writing to
GWA F80AH. A write to F809H will also work if the
SYNCO pin is externally connected to the SYNCI pin.
register IWA *00AH bit 31.
the μPHold bit in register IWA *00AH bit 31).
Filter Compute Engine.
July 13, 2007
FN6013.3