MACH211-15VC Lattice, MACH211-15VC Datasheet - Page 10

• Manufacturer Part Number: MACH211-15VC
• Description: CPLD MACH 2 Family 2.5K Gates 64 Macro Cells 66.6MHz EECMOS Technology 5V 44-Pin TQFP
• Manufacturer: Lattice

Specifications of MACH211-15VC

• Package: 44TQFP
• Family Name: MACH 2
• Device System Gates: 2500
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 32
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 66.6 MHz
• Number Of Product Terms Per Macro: 16
• Operating Temperature: 0 to 70 °C

10
From Logic
Allocator
Allocator
Allocator
From
Logic
From
Logic
CLK n
CLK 0
CLK n
CLK 0
Sum of Products
To Switch
To Switch
Asynchronous
Asynchronous
To Switch
Matrix
IC Allocator
Matrix
From Logic
PAL-Block
PAL-Block
Matrix
Preset
Reset
n
n
CLK 0
CLK n
n
a. Combinatorial
c. T-type register
e. Latch
Figure 6. Buried Macrocell Configurations (MACH 2 only)
Switch
Matrix
To
Figure 5. Buried Macrocell (MACH 2 only)
L
G
T
AP
AR
AP
AR
Q
Q
MACH 1 & 2 Families
1
0
From Logic
D/T/L
Allocator
CLK n
CLK 0
AP
AR
CLÂK n
CLKÂ 0
To Switch
CLK n
To Switch
CLK 0
Matrix
Matrix
Q
To Switch
Matrix
n
d. Input register
1
b. D-type register
0
f. Input latch
L
G
D
AP
AR
AP
AR
Q
Q
From I/O Pin
D
AP
AR
Q
From I/O
Cell
From I/O
Cell
14051K-030
14051K-006