MACH211-15VC Lattice, MACH211-15VC Datasheet - Page 12

• Manufacturer Part Number: MACH211-15VC
• Description: CPLD MACH 2 Family 2.5K Gates 64 Macro Cells 66.6MHz EECMOS Technology 5V 44-Pin TQFP
• Manufacturer: Lattice

Specifications of MACH211-15VC

• Package: 44TQFP
• Family Name: MACH 2
• Device System Gates: 2500
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 32
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 66.6 MHz
• Number Of Product Terms Per Macro: 16
• Operating Temperature: 0 to 70 °C

SPEEDLOCKING FOR GUARANTEED FIXED TIMING
The unique MACH 1 & 2 architecture is designed for high performance—a metric that is met in
both raw speed, and even more importantly, guaranteed fixed speed. The design of the switch
matrix and PAL blocks guarantee a fixed pin-to-pin delay that is independent of the logic required
by the design. Other non-Lattice/Vantis CPLDs incur serious timing delays as product terms expand
beyond their typical 4 or 5 product term limits (Figure 8). Speed and SpeedLocking combine to
give designers easy access to the performance required in today’s designs.
12
(Common to bank of
Output Enable
Product Terms
• Patented Architecture
• Path Independent
• Logic/Routing Independent
• Guaranteed Fixed Timing
• Up to 16 Product Terms per Output
I/O Cells)
t PD (ns)
MACH 1 & 2 SpeedLocking
Figure 8. Timing in MACH 1 & 2 vs. Non-MACH Devices
11
10
9
8
7
6
5
From Output
Macrocell
To Switch
Shared Expander Delay
5 ns
Matrix
8.8 ns
V
Parallel Expander Delay
5 PT
MACH 1 & 2 Families
CC
Figure 7. I/O Cell
5.8 ns
SpeedLocking
Product Terms
0 1
1 1
1 0
0 0
10 PT
6.6 ns
• Variable
• Path Dependent
• Logic/Routing Dependent Delays
• Unpredictable
• 4-5 Product Terms before Delays
15 PT
10.4 ns
Non-MACH
Non-MACH
7.4 ns
MACH 1 & 2
(MACH 2 only)
Macrocell
To Buried
14051K-007
14051K-001