MACH211-15VC Lattice, MACH211-15VC Datasheet - Page 42

• Manufacturer Part Number: MACH211-15VC
• Description: CPLD MACH 2 Family 2.5K Gates 64 Macro Cells 66.6MHz EECMOS Technology 5V 44-Pin TQFP
• Manufacturer: Lattice

Specifications of MACH211-15VC

• Package: 44TQFP
• Family Name: MACH 2
• Device System Gates: 2500
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 32
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 66.6 MHz
• Number Of Product Terms Per Macro: 16
• Operating Temperature: 0 to 70 °C

68-PIN PLCC CONNECTION DIAGRAM (MACH221-7/10/12/15)
Top View
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I
I/O
V
42
CC
= Input
= Input/Output
= Supply Voltage
CLK0/I0
CLK1/I1
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
GND
VCC
I/O7
I/O8
I/O9
I2
I3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28
9 8
29 30 31 32 33 34
Block D
7 6 5 4 3 2
MACH 1 & 2 Families
Block A
68-Pin PLCC
35 36 37 38 39 40 41 42 43
1 68 67 66 65 64 63 62 61
Block E
Block H
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I7
I6
I/O41
I/O40
I/O39
I/O38
I/O37
I/O36
GND
VCC
CLK3/I5
CLK2/I4
I/O35
I/O34
I/O33
I/O32
I/O31
14051K-025