MACH211-15VC Lattice, MACH211-15VC Datasheet - Page 44

• Manufacturer Part Number: MACH211-15VC
• Description: CPLD MACH 2 Family 2.5K Gates 64 Macro Cells 66.6MHz EECMOS Technology 5V 44-Pin TQFP
• Manufacturer: Lattice

Specifications of MACH211-15VC

• Package: 44TQFP
• Family Name: MACH 2
• Device System Gates: 2500
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 32
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 66.6 MHz
• Number Of Product Terms Per Macro: 16
• Operating Temperature: 0 to 70 °C

84-PIN PLCC CONNECTION DIAGRAM (MACH231-6/7/10/12/15)
Top View
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I
I/O
V
44
CC
= Input
= Input/Output
= Supply Voltage
CLK 0 /I 0
CLK 1 /I 1
I/O10
I/O11
I/O12
I/O14
I/O13
I/O15
I/O16
I/O18
I/O22
I/O17
I/O19
I/O20
I/O21
I/O23
GND
GND
V CC
I/O9
I/O8
12
13
14
15
17
16
18
19
20
21
22
23
24
26
28
29
31
32
25
27
30
11
33
10
34
35
9
Block D
36
8
Block A
37
7
38
6
39
5
MACH 1 & 2 Families
40
4
84-Pin PLCC
41
3
42
2
43
1
84
44
83
45
82
46
81
47
Block E
80
48
Block H
79
49
78
50
77
51
76
52
75
53
74
73
72
71
70
69
68
67
56
66
65
64
63
62
61
60
59
58
57
55
54
I/O55
GND
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
CLK 3 /I 4
GND
I/O48
V CC
CLK 2 /I 3
I/O47
I/O46
I/O44
I/O43
I/O42
I/O41
I/O40
I/O45
14051K-027