CS5396-KS Cirrus Logic Inc, CS5396-KS Datasheet - Page 25

• Manufacturer Part Number: CS5396-KS
• Description: ADC Dual Delta-Sigma 96KSPS 24-Bit Serial 28-Pin SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5396-KS

• Package: 28SOIC
• Resolution: 24 Bit
• Sampling Rate: 96 KSPS
• Architecture: Delta-Sigma
• Number Of Analog Inputs: 2
• Digital Interface Type: Serial (SPI)
• Input Type: Voltage
• Sample And Hold: Yes
• Polarity Of Input Voltage: Bipolar

REGISTER DESCRIPTION
** “default” ==> bit status after power-up-sequence
Analog control (address 00000001)
FSTART (Frame start)Default = ‘0’.
GNDCAL (Ground calibration enable)
AAPD (Analog Section of modulator in power down)
ADPD (Digital Section of modulator in power down)
TEST BIT
Mode (address 00000010)
128x/64x
CAL (System calibration enable)
Change_sign (Change Sign enable)
_LR/LL (Left-Right output disable) Default = ‘0’.
DS229PP2
128x/64x
fstart
7
0
7
0
gndcal
cal
This bit must be set to ‘1’ to synchronize the modulator output and the decimation filter input
and is automatically reset to ‘0’ after a “fstart” pulse is sent to the analog and digital block.
Default = ‘0’.
Modulator input is tied to internal “Vcom” when this bit is ‘1’.
Default = ‘0’.
The analog section of the modulator is in power down mode when aapd = ‘1’.
Default = ‘0’.
The digital section on the modulator is in power down mode when adpd = ‘1’.
Must remain at 0.
6
0
Oversampling ratio is 128 when this bit is ‘1’ and 64 when this bit is ‘0’.
Default = ‘0’.
Setting this bit to ‘1’ will initiate calibration.
This bit is automatically reset to ‘0’ following calibration.
Default = ‘0’.
A ‘1’ will interchange the analog input paths within each channel resulting in a phase inversion
of the analog signal. This bit applies to both channels.
SDATA2 will output the Left and Right channel data from the sdata2 source as described else-
where in the data sheet.
If this bit is set to ‘1’, the Left channel data from sdata1 source and sdata2 source (stored in
Audio port register) will be sent out in SDATA1. SDATA2 will output all the Right channel data.
Default =’0’.
Default = ‘0’.
If this bit is ‘0’, SDATA1 will output the Left and Right channel data from the sdata1 source and
6
0
change_sign
aapd
5
0
5
0
_LR/LL
adpd
4
0
4
0
_hpen
1bit
3
0
3
0
s/_m
2
2
0
CS5396 CS5397
DFS
1
1
0
mute
0
0
0
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