CS5396-KS Cirrus Logic Inc, CS5396-KS Datasheet - Page 32

• Manufacturer Part Number: CS5396-KS
• Description: ADC Dual Delta-Sigma 96KSPS 24-Bit Serial 28-Pin SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5396-KS

• Package: 28SOIC
• Resolution: 24 Bit
• Sampling Rate: 96 KSPS
• Architecture: Delta-Sigma
• Number Of Analog Inputs: 2
• Digital Interface Type: Serial (SPI)
• Input Type: Voltage
• Sample And Hold: Yes
• Polarity Of Input Voltage: Bipolar

AINL-, AINL+ - Differential Left Channel Analog Inputs, Pin 4,5.
Analog Outputs
VCOM - Common Mode Voltage Output, Pin 2.
VREF - Voltage Reference Output, Pin 1.
Digital Inputs
ADCTL - Analog Control Input, Pin 6.
MCLKA - Analog Section Input Clock, Pin 7.
MCLKD - Digital Section Input Clock, Pin 20.
Digital Input Pin Definitions for Stand-Alone MODE
DFS - Digital Format Select, Pin 18.
PDN - Power-Down, Pin 19.
32
Analog input connections for the left channel differential inputs. Nominally 4.0 Vpp differential
for full-scale digital output.
Nominally +2.5 volts. Requires a 100 F electrolytic capacitor in parallel with 0.1 F ceramic
capacitor for decoupling to AGND. Caution is required if this output is to be used to bias the
analog input buffer circuits. Refer to text.
Nominally +4.0 volts. Requires a 470 F electrolytic capacitor in parallel with 0.1 F ceramic
capacitor for decoupling to AGND.
Must be connected to DACTL. This signal enables communication between the analog and
digital circuits.
This clock is internally divided and controls the delta-sigma modulators. The required MCLKA
frequency is determined by the desired output sample rate (Fs). MCLKA of 24.576 MHz
corresponds to an Fs of 96 kHz in 64
Mode.
MCLKD clocks the digital filter and must be connected to MCLKA. The required MCLKD
frequency is determined by the desired output sample rate (Fs). MCLKD of 24.576 MHz
corresponds to an Fs of 96 kHz in 64
Mode.
The relationship between LRCK, SCLK and SDATA is controlled by the DFS pin. When high,
the serial output data format is I
When high, the device enters power-down. Upon returning low, the device enters normal
operation. Calibration of the device is required following release of power-down.
2
S compatible. The serial data format is left-justified when low.
x
x
Oversampling Mode and 48 kHz in 128
Oversampling Mode and 48 kHz in 128
CS5396 CS5397
x
x
Oversampling
Oversampling
DS229PP2