PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 4

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

TABLE OF CONTENTS
1
2
3
4
5
6
1.1
1.2
1.3
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
3.1
3.2
5.1
5.2
6.1
6.2
6.3
INTRODUCTION ........................................................................................................................ 10
PIN DEFINITIONS...................................................................................................................... 12
MODE SELECTION AND PIN STRAPPING.......................................................................... 16
FORWARD AND REVERSE BRIDGING................................................................................ 18
PCI EXPRESS FUNCTIONAL OVERVIEW........................................................................... 20
CONFIGURATION REGISTER ACCESS............................................................................... 21
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.3.12
6.3.13
6.3.14
6.3.15
6.3.16
Pericom Semiconductor - Confidential
PCI EXPRESS FEATURES................................................................................................... 10
PCI FEATURES..................................................................................................................... 11
GENERAL FEATURES ........................................................................................................ 11
SIGNAL TYPES .................................................................................................................... 12
PCI EXPRESS SIGNALS ...................................................................................................... 12
PCI SIGNALS ........................................................................................................................ 12
MODE SELECT AND STRAPPING SIGNALS................................................................... 15
JTAG BOUNDARY SCAN SIGNALS ................................................................................. 15
MISCELLANEOUS SIGNALS ............................................................................................. 15
POWER AND GROUND PINS............................................................................................. 15
PIN ASSIGNMENTS............................................................................................................. 16
FUNCTIONAL MODE SELECTION ................................................................................... 17
PIN STRAPPING ................................................................................................................... 17
TLP STRUCTURE................................................................................................................. 20
VIRTUAL ISOCHRONOUS OPERATION.......................................................................... 20
CONFIGURATION REGISTER MAP.................................................................................. 21
PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP ........................................... 23
PCI CONFIGURATION REGISTERS.................................................................................. 25
VENDOR ID – OFFSET 00h ................................................................................................................ 25
DEVICE ID – OFFSET 00h.................................................................................................................. 25
COMMAND REGISTER – OFFSET 04h .............................................................................................. 25
PRIMARY STATUS REGISTER – OFFSET 04h................................................................................... 26
REVISION ID REGISTER – OFFSET 08h ........................................................................................... 27
CLASS CODE REGISTER – OFFSET 08h ........................................................................................... 27
CACHE LINE SIZE REGISTER – OFFSET 0Ch.................................................................................. 28
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch .................................................................. 28
PRIMARY HEADER TYPE REGISTER – OFFSET 0Ch ...................................................................... 28
RESERVED REGISTERS – OFFSET 10h TO 17h................................................................................ 28
PRIMARY BUS NUMBER REGISTER – OFFSET 18h ........................................................................ 28
SECONDARY BUS NUMBER REGISTER – OFFSET 18h .................................................................. 28
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h .............................................................. 28
SECONDARY LATENCY TIME REGISTER – OFFSET 18h................................................................ 29
I/O BASE REGISTER – OFFSET 1Ch.................................................................................................. 29
I/O LIMIT REGISTER – OFFSET 1Ch................................................................................................. 29
Page 4 of 78
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL