PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 69

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

10.3 EEPROM AUTOLOAD CONFIGURATION
When SM bus interface is selected, SMBCLK pin is an input for the clock of SMbus and SMBDAT pin is an open
drain buffer that requires external pull-up resistor for proper operation.
The SM Bus Commands of PI7C9X111SL are provided below:
Write Word protocol (PEC Disabled):
S + Slave Address[7:1] + 0(Wr) + A + 0000_1000 + A + Bus Number[7:0] + A + Device/Function + A + P
S + Slave Address[7:1] + 0(Wr) + A + 0000_1000 + A + Reg Number[7:0] + A + Reg Number[15:8] + A + P
S + Slave Address[7:1] + 0(Wr) + A + 0000_1000 + A + Data[7:0] + A + Data[15:8] + A + P
Read Word protocol (PEC Disabled):
S + Slave Address[7:1] + 0(Wr) + A + 0000_1000 + A + Bus Number[7:0] + A + Device/Function + A + P
S + Slave Address[7:1] + 0(Wr) + A + 0000_1000 + A + Reg Number[7:0] + A + Reg Number[15:8] + A + P
S + Slave Address[7:1] + 0(Wr) + A + 0000_1000 + A + Sr + Slave Address[7:1] + 1(Rd) + A + Data[7:0] + A +
Data[15:8] + N + P
Where Bus number and device/Function filed have to be 0x00. For additional info on SMBus programming, please
refer to section 7 of datasheets.
Pericom Semiconductor - Confidential
EEPROM Byte
Addresses
00-01h
02h
03h
04-05h
06-07h
08h
09h
0A-0Bh
0Ch
0D-0Eh
0F-10h
11-14h
15-18h
19-1Ah
1Bh
1C-1Eh
1F-21h
22-25h
26-29h
2A-2Dh
Cfg Offset
00-01h
02-03h
08h
09h
0A-0Bh
34h
40-41h
42-43h
48-4Bh
68-6Bh
81-82h
108h
91-93h
A1-A3h
A4-A7h
A8-ABh
AC-AFh
Description
EEPROM signature: Autoload will only proceed if it reads a value
of 1516h on the first word loaded.
Region Enable: Enables or disables certain regions of PCI
configuration space from being loaded from the EEPROM.
Enable Miscellaneous functions: (for transparent mode only)
bit is set, 9x111 will change the bit 2 of 3Eh into RO, and ISA
enable feature will not be available.
Vendor ID
Device ID
Revision ID
Class Code: low bytes of Class Code register
Class Code higher bytes: upper bytes of Class Code register
Capability Pointer
PCI data prefetching control
Chip control 0
Arbiter Mode/Enable/Priority
PCIE Transmitter/Receiver control
PCIX Capability
Uncorrectable Error Mask register
Power Management Capability
SI Capability
Secondary Clock and Clkrun Control
SSID/SSVID Capability
SSID/SSVID
Page 69 of 78
bit 0: reserved
bit 4-1: 0000=stop autoload at offset 0Bh: Group 1
bit 7-5: reserved
bit 0: ISA Enable control bit write protect: when this
0001=stop autoload at offset 67h: Group 2
0011=stop autoload at offset AFh: Group 3
0111=stop autoload at offset D7h: Group 4
other combinations are undefined
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL