PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 6

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

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Pericom Semiconductor - Confidential
NEXT POINTER REGISTER – OFFSET A8h....................................................................................... 47
RESERVED REGISTER – OFFSET A8h .............................................................................................. 48
SUBSYSTEM VENDOR ID REGISTER – OFFSET ACh...................................................................... 48
SUBSYSTEM ID REGISTER – OFFSET ACh ...................................................................................... 48
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET B0h .............................................................. 48
NEXT CAPABILITY POINTER REGISTER – OFFSET B0h ................................................................ 48
PCI EXPRESS CAPABILITY REGISTER – OFFSET B0h ................................................................... 48
DEVICE CAPABILITY REGISTER – OFFSET B4h............................................................................. 48
DEVICE CONTROL REGISTER – OFFSET B8h................................................................................. 50
DEVICE STATUS REGISTER – OFFSET B8h..................................................................................... 50
LINK CAPABILITY REGISTER – OFFSET BCh ................................................................................. 51
LINK CONTROL REGISTER – OFFSET C0h...................................................................................... 51
LINK STATUS REGISTER – OFFSET C0h.......................................................................................... 51
SLOT CAPABILITY REGISTER – OFFSET C4h ................................................................................. 52
SLOT CONTROL REGISTER – OFFSET C8h ..................................................................................... 52
SLOT STATUS REGISTER – OFFSET C8h ......................................................................................... 53
XPIP CONFIGURATION REGISTER 0 – OFFSET CCh..................................................................... 53
XPIP CONFIGURATION REGISTER 1 – OFFSET D0h ..................................................................... 53
XPIP CONFIGURATION REGISTER 2 – OFFSET D4h ..................................................................... 53
L0 ENTER L1 WAITING PERIOD COUNTER – OFFSET D4h .......................................................... 55
CAPABILITY ID REGISTER – OFFSET D8h ...................................................................................... 55
NEXT POINTER REGISTER – OFFSET D8h ...................................................................................... 55
VPD REGISTER – OFFSET D8h ......................................................................................................... 55
VPD DATA REGISTER – OFFSET DCh.............................................................................................. 55
RESERVED REGISTERS – OFFSET E0h – ECh ................................................................................. 56
MESSAGE SIGNALED INTERRUPTS ID REGISTER – F0h............................................................... 56
NEXT CAPABILITIES POINTER REGISTER – F0h............................................................................ 56
MESSAGE CONTROL REGISTER – OFFSET F0h ............................................................................. 56
MESSAGE ADDRESS REGISTER – OFFSET F4h .............................................................................. 56
MESSAGE UPPER ADDRESS REGISTER – OFFSET F8h................................................................. 56
MESSAGE DATA REGISTER – OFFSET FCh..................................................................................... 57
ADVANCE ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h .............................. 57
ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER – OFFSET 100h .................. 57
NEXT CAPABILITY OFFSET REGISTER – OFFSET 100h ................................................................ 57
UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h ................................................... 57
UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h ...................................................... 57
UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch............................................... 58
CORRECTABLE ERROR STATUS REGISTER – OFFSET 110h......................................................... 58
CORRECTABLE ERROR MASK REGISTER – OFFSET 114h ............................................................ 58
ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h........................ 59
HEADER LOG REGISTER 1 – OFFSET 11Ch .................................................................................... 59
HEADER LOG REGISTER 2 – OFFSET 120h..................................................................................... 59
HEADER LOG REGISTER 3 – OFFSET 124h..................................................................................... 59
HEADER LOG REGISTER 4 – OFFSET 128h..................................................................................... 59
SECONDARY UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 12Ch ........................... 59
SECONDARY UNCORRECTABLE ERROR MASK REGISTER – OFFSET 130h ............................... 60
SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 134h ........................ 60
SECONDARY ERROR CAPABILITY AND CONTROL REGISTER – OFFSET 138h.......................... 61
SECONDARY HEADER LOG REGISTER – OFFSET 13Ch – 148h.................................................... 61
RESERVED REGISTER – OFFSET 14Ch ............................................................................................ 61
VC CAPABILITY ID REGISTER – OFFSET 150h ............................................................................... 61
VC CAPABILITY VERSION REGISTER – OFFSET 150h ................................................................... 61
Page 6 of 78
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL