PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 45

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

6.3.60 POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h
6.3.61 PCI-TO-PCI SUPPORT EXTENSION REGISTER – OFFSET 94h
Pericom Semiconductor - Confidential
BIT
19
20
21
24:22
25
26
31:27
BIT
1:0
7:2
8
12:9
14:13
15
BIT
FUNCTION
PME Clock
Reserved
Device Specific Initialization
(DSI)
AUX Current
D1 Power Management
D2 Power Management
PME_L Support
FUNCTION
Power State
Reserved
PME Enable
Data Select
Data Scale
PME Status
FUNCTION
RWCS
TYPE
TYPE
TYPE
RWS
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Page 45 of 78
DESCRIPTION
PME clock is not required for PME_L generation
Reset to 0
Reset to 0
DSI – no special initialization of this function beyond the standard PCI
configuration header is required following transition to the D0 un-initialized
state
Reset to 0
000: 0mA
001: 55mA
010: 100mA
011: 160mA
100: 220mA
101: 270mA
110: 320mA
111: 375mA
Reset to 001
D1 power management is not supported
Reset to 0
D2 power management is not supported
Reset to 0
PME_L is supported in D3 cold, D3 hot, and D0 states.
Reset to 11001
DESCRIPTION
Power State is used to determine the current power state of PI7C9X111SL.
If a non-implemented state is written to this register, PI7C9X111SL will
ignore the write data. When present state is D3 and changing to D0 state by
programming this register, the power state change causes a device reset
without activating the RESET_L of PCI bus interface
00: D0 state
01: D1 state not implemented
10: D2 state not implemented
11: D3 state
Reset to 00
Reset to 000000
0: PME_L assertion is disabled
1: PME_L assertion is enabled
Reset to 0
Data register is not implemented
Reset to 0000
Data register is not implemented
Reset to 00
PME_L is supported
Reset to 0
DESCRIPTION
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL