SI3050-KT Silicon Laboratories Inc, SI3050-KT Datasheet - Page 31

• Manufacturer Part Number: SI3050-KT
• Description: IC VOICE DAA GCI/PCM/SPI 20TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: Chipsetr

Specifications of SI3050-KT

• Package / Case: 20-TSSOP
• Function: Data Access Arrangement (DAA)
• Interface: PCM, Serial, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 8.5mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Includes: Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
• Product: Modem Chip
• Supply Voltage (min): 3 V
• Supply Current: 8.5 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

active (PDL=0) and the device is not off-hook or in
on-hook line monitor mode, the ring data is presented
on DTX. The waveform on DTX depends on the state of
the RFWE bit.
When RFWE is 0, DTX is –32768 (0x8000) while the
RNG1-RNG2 voltage is between the thresholds. When
a ring is detected, DTX transitions to +32767 when the
ring signal is positive, then goes back to –32768 when
the ring is near 0 and negative. Thus a near square
wave is presented on DTX that swings from –32768 to
+32767 in cadence with the ring signal.
When RFWE is 1, DTX sits at approximately +1228
while the RNG1-RNG2 voltage is between the
thresholds. When the ring becomes positive, DTX
transitions to +32767. When the ring signal goes near 0,
DTX remains near 1228. As the ring becomes negative,
the DTX transitions to –32768. This repeats in cadence
with the ring signal.
To observe the ring signal on DTX, watch the MSB of
the data. The MSB toggles at the same frequency as
the ring signal independent of the ring detector mode.
This method is adequate for determining the ring
frequency.
Ring Validation
Ring validation prevents false triggering of a ring
detection by validating the ring parameters. Invalid
signals, such as a line-voltage change when a parallel
handset goes off-hook, pulse dialing, or a high-voltage
line test are ignored. Ring validation can be enabled
during normal operation and in low-power sleep mode
when a valid external PCLK signal is supplied.
The ring validation circuit operates by calculating the
time between alternating crossings of positive and
negative ring thresholds to validate that the ring
frequency is within tolerance. High and low frequency
tolerances are programmable in the RAS[5:0] and
RMX[5:0] fields. The RCC[2:0] bits define how long the
ring signal must be within tolerance.
Once the duration of the ring frequency is validated by
the RCC bits, the circuitry stops checking for frequency
tolerance and begins checking for the end of the ring
signal, which is defined by a lack of additional threshold
crossings for a period of time configured by the
RTO[3:0] bits. When the ring frequency is first validated,
a timer defined by the RDLY[2:0] bits is started. If the
RDLY[2:0] timer expires before the ring timeout, then
the ring is validated and a valid ring is indicated. If the
ring timeout expires before the RDLY[2:0] timer, a valid
ring is not indicated.
Ring validation requires the following five parameters:
!
Timeout parameter to place a lower limit on the
Rev. 1.0
!
!
!
!
The RNGV bit (Register 24, bit 7) enables or disables
the ring validation feature in both normal operating
mode and low-power sleep mode.
Ring validation affects the behavior of the RDT status
bit, the RDTI interrupt, the INT pin, and the RGDT pin.
1. When ring validation is enabled, the status bit seen in the
2. The RDTI interrupt fires when a validated ring occurs. If
3. The INT pin follows the RDTI bit with configurable polarity.
4. The RGDT pin can be configured to follow the ringing
Ringer Impedance and Threshold
The ring detector in a typical DAA is ac coupled to the
line with a large 1 µ F, 250 V decoupling capacitor. The
ring detector on the Si3018/19 is resistively coupled to
the line. This coupling produces a high ringer
impedance to the line of approximately 20 M Ω to meet
the majority of country PTT specifications including FCC
and TBR21.
Several countries including Poland, South Africa, and
Slovenia require a maximum ringer impedance that can
be met with an internally-synthesized impedance by
setting the RZ bit (Register 16). Certain countries also
specify ringer thresholds differently. The RT and RT2
bits (Register 16 and Register 17, respectively) select
between three different ringer thresholds: 15 V ±10%,
21 V ±10%, and 45 V ±10%. These three settings
frequency of the ring signal (the RAS[5:0] bits in
Register 24). The frequency is measured by
calculating the time between crossings of positive
and negative ring thresholds.
Minimum count to place an upper limit on the
frequency (the RMX[5:0] bits in Register 22).
Time interval over which the ring signal must be the
correct frequency (the RCC[2:0] bits in Register 23).
Timeout period that defines when the ring pulse has
ended based on the most recent ring threshold
crossing.
Delay period between when the ring signal is
validated and when a valid ring signal is indicated to
help accommodate distinctive ringing.
RDT read-only bit (r5.2), represents the detected envelope
of the ring. The ring validation parameters are configurable
so that this envelope may remain high throughout a
distinctive-ring sequence.
RDI is zero (default), the interrupt occurs on the rising
edge of RDT. If RDI is set, the interrupt occurs on both
rising and falling edges of RDT.
signal envelope detected by the ring validation circuit by
setting RFWE to 0. If RFWE is set to 1, the RGDT pin
follows an unqualified ring detect one-shot signal initiated
by a ring-threshold crossing and terminated by a fixed
counter timeout of approximately 5 seconds. (This
information is shown in Register 18).
Si3050
31