AT86RF232 Atmel Corporation, AT86RF232 Datasheet - Page 16

• Manufacturer Part Number: AT86RF232
• Manufacturer: Atmel Corporation

Specifications of AT86RF232

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -100
• Receive Current Consumption (ma): 11.8
• Transmit Current Consumption (ma): 13.8
• Link Budget (dbm): 103

6.2 SPI Protocol
Table 6-2. SPI Command Byte Definition.
6.2.1 Register Access Mode
16
Bit 7
1
1
0
0
0
0
AT86RF232
Bit 6
0
1
0
1
0
1
Bit 5
1
1
0
0
Bit 4
Referring to
edge of the SCLK signal and the output is set at the falling edge of SCLK. The signal
must be stable before and after the rising edge of SCLK as specified by t
to
This SPI operational mode is commonly known as “SPI mode 0”.
Each SPI sequence starts with transferring a command byte from the SPI master via
MOSI (see
and additional mode-dependent information.
Each SPI transfer returns bytes back to the SPI master on MISO. The content of the
first byte (see value “PHY_STATUS“ in
reset. To transfer status information of the radio transceiver to the microcontroller, the
content of the first byte can be configured with register bits SPI_CMD_MODE
(register 0x04, TRX_CTRL_1). For details, refer to
In
MOSI are ignored by the radio transceiver, but need to have a valid logic level. Return
values on MISO stated as XX shall be ignored by the microcontroller.
The different access modes are described within the following sections.
A register access mode is a two-byte read/write operation initiated by /SEL = L. The first
transferred byte on MOSI is the command byte including an identifier bit (bit[7] = 1), a
read/write select bit (bit[6]), and a 6-bit register address.
On read access, the content of the selected register address is returned in the second
byte on MISO (see
Figure 6-4. Packet Structure - Register Read Access.
MOSI
MISO
Note:
Note:
Section 12.4
Figure 6-4
Register address [5:0]
Register address [5:0]
1
Bit 3
1.
1.
Table
byte 1 (command byte)
0
Figure 6-2
PHY_STATUS
Each SPI access can be configured to return radio controller status information
(PHY_STATUS) on MISO, for details refer to
to
When both /SEL and /RST are active, the MISO output driver is also enabled.
parameters.
ADDRESS[5:0]
Figure 6-14
reserved
reserved
reserved
reserved
6-2) with MSB first. This command byte defines the SPI access mode
Bit 2
Figure
and
(1)
6-4).
Figure 6-3
Bit 1
and the following chapters logic values stated with XX on
READ DATA[7:0]
byte 2 (data byte)
Atmel AT86RF232 MOSI is sampled at the rising
Bit 0
Figure 6-4
XX
Access Mode
Register access
Frame Buffer access
SRAM access
Section
to
Section
Figure
6.3.1.
6.3.
6-14) is set to zero after
8321A–MCU Wireless–10/11
Access Type
Read access
Write access
Read access
Write access
Read access
Write access
3
and t
4
, refer