AT86RF232 Atmel Corporation, AT86RF232 Datasheet - Page 59

• Manufacturer Part Number: AT86RF232
• Manufacturer: Atmel Corporation

Specifications of AT86RF232

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -100
• Receive Current Consumption (ma): 11.8
• Transmit Current Consumption (ma): 13.8
• Link Budget (dbm): 103

8321A–MCU Wireless–10/11
Overview
The implemented TX_ARET algorithm is shown in
In TX_ARET mode, the Atmel AT86RF232 first executes the CSMA-CA algorithm, as
defined by IEEE 802.15.4–2006, Section 7.5.1.4, initiated by a transmit start event. If
the channel is IDLE a frame is transmitted from the Frame Buffer. If the
acknowledgement frame is requested the radio transceiver additionally checks for an
ACK reply.
The completion of the TX_ARET
IRQ_3 (TRX_END) interrupt.
Description
Configuration and address bits are to be set in TRX_OFF or PLL_ON state prior to
switching to TX_ARET mode. It is further recommended to transfer the PSDU data to
the Frame Buffer in advance. The transaction is started by either using
pin 11 (SLP_TR), refer to
TRX_CMD (register 0x02, TRX_STATE).
If the CSMA-CA detects a busy channel, it is retried as specified by the register bits
MAX_CSMA_RETRIES (register 0x2C, XAH_CTRL_0). In case that CSMA-CA does
not detect a clear channel after MAX_CSMA_RETRIES, it aborts the TX_ARET
transaction, issues interrupt IRQ_3 (TRX_END), and set the value of the register bits
TRAC_STATUS to CHANNEL_ACCESS_FAILURE.
During transmission of a frame the radio transceiver parses bit 5 (ACK Request) of the
MAC header (MHR) frame control field of the PSDU data (PSDU octet #1) to be
transmitted to check if an ACK reply is expected.
If an ACK is expected, the radio transceiver automatically switches into receive mode to
wait for a valid ACK reply. After receiving an ACK frame the Frame Pending subfield of
that frame is parsed and the status register bits TRAC_STATUS are updated
accordingly, refer to
Buffer content. Transmit data in the Frame Buffer is not changed during the entire
TX_ARET transaction. Received frames other than the expected ACK frame are
discarded.
If no valid ACK is received or after timeout of 54 symbol periods (864µs), the radio
transceiver retries the entire transaction, (including CSMA-CA) until the maximum
number of retransmissions (as set by the register bits MAX_FRAME_RETRIES
(register 0x2C, XAH_CTRL_0)) is exceeded.
The current CSMA-CA and frame retransmission counter values of an ongoing
TX_ARET transaction can be retrieved by the register bits ARET_FRAME_RETRIES
and ARET_CSMA_RETRIES (register 0x19, XAH_CTRL_2).
Additionally to the RX Frame Time stamping via pin 10 (DIG2), a TX Frame Time
stamping within TX_ARET mode can be activated, if the register bits IRQ_2_EXT_EN
(register 0x04, TRX_CTRL_1) and ARET_TX_TS_EN (register 0x17, XAH_CTRL_1)
are set to one, see
After that, the microcontroller may read the value of the register bits TRAC_STATUS
(register 0x02, TRX_STATE) to verify whether the transaction was successful or not.
The register bits are set according to the following cases, additional exit codes are
described in
Section
Section
7.2.6:
Table
Section
7-12. This receive procedure does not overwrite the Frame
11.4.
6.5, or writing a TX_START command to register bits
transmit transaction is indicated by an
Figure
7-14.
AT86RF232
59