M42800A Atmel Corporation, M42800A Datasheet - Page 11

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7. Product Overview
7.1
7.2
7.3
7.4
1779ES–ATARM–14-Apr-06
Power Supply
Input/Output Considerations
Operating Modes
Clock Generator
The AT91M42800A has three kinds of power supply pins:
VDDCORE and VDDIO pins allow core power consumption to be reduced by supplying it with a
lower voltage than the I/O lines. The VDDCORE pins must never be powered at a voltage
greater than the supply voltage applied to the VDDIO.
The VDDPLL pin is used to supply the oscillator and both PLLs. The voltage applied on these
pins is typically 3.3V, and it must not be lower than VDDCORE.
Typical supported voltage combinations are shown in the following table:
After the reset, the peripheral I/Os are initialized as inputs to provide the user with maximum
flexibility. It is recommended that in any application phase, the inputs to the AT91M42800A
microcontroller be held at valid logic levels to minimize the power consumption.
The AT91M42800A has two pins dedicated to defining MODE0 and MODE1 operating modes.
These pins allow the user to enter the device in Boundary Scan mode. They also allow the user
to run the processor from the on-chip oscillator and from an external clock by bypassing the on-
chip oscillator. The last mode is reserved for test purposes. A chip reset must be performed
(NRST and NTRST) after MODE0 and/or MODE1 have been changed.
The AT91M42800A microcontroller embeds a 32.768 kHz oscillator that generates the Slow
Clock (SLCK). This on-chip oscillator can be bypassed by setting the correct logical level on
MODE0 and MODE1 pins, as shown above. In this case, SLCK equals XIN.
Pins
VDDCORE
VDDIO
VDDPLL
• VDDCORE pins, which power the chip core
• VDDIO pins, which power the I/O lines
• VDDPLL pins, which power the oscillator and PLL cells
MODE0
0
0
1
1
MODE1
0
1
0
1
Operating Mode
Normal operating mode by using the on-chip oscillator
Boundary Scan Mode
Normal operating mode by using an external clock on XIN
Reserved for test
3.3V
5.0V
3.3V
Nominal Supply Voltages
AT91M42800A
3.0V or 3.3V
3.0V or 3.3V
3.0V or 3.3V
11