M42800A Atmel Corporation, M42800A Datasheet - Page 13

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.5.3
7.6
7.6.1
7.6.2
1779ES–ATARM–14-Apr-06
Emulation Functions
Watchdog Reset
Tri-state Mode
Embedded ICE
Figure 7-1.
Notes:
In order to benefit from the separation of NRST and NTRST during the debug phase of develop-
ment, the user must independently manage both signals as shown in example (1) of
above. However, once debug is completed, both signals are easily managed together during
production as shown in example (2) of
The internally generated watchdog reset has the same effect as the NRST pin, except that the
pins BMS and NTRI are not sampled. Boot mode and Tri-state mode are not updated. The
NRST pin has priority if both types of reset coincide.
The AT91M42800A provides a Tri-state mode, which is used for debug purposes in order to
connect an emulator probe to an application board. In Tri-state mode the AT91M42800A contin-
ues to function, but all the output pin drivers are tri-stated.
To enter Tri-state mode, the pin NTRI must be held low during the last 10 SLCK clock cycles
before the rising edge of NRST. For normal operation, the pin NTRI must be held high during
reset, by a resistor of up to 400 k . NTRI must be driven to a valid logic value during reset.
NTRI is multiplexed with Parallel I/O PA9 and USART 1 serial data transmit line TXD1.
Standard RS232 drivers generally contain internal 400 k pull-up resistors. If TXD1 is connected
to one of these drivers, this pull-up will ensure normal operation, without the need for an addi-
tional external resistor.
ARM standard embedded in-circuit emulation is supported via the JTAG/ICE port. It is con-
nected to a host computer via an embedded ICE Interface.
Embedded ICE mode is selected when MODE1 is low.
It is not possible to switch directly between ICE and JTAG operations. A chip reset must be per-
formed (NRST and NTRST) after MODE0 and/or MODE1 have/has been changed. The reset
input to the Embedded ICE (NTRST) is provided separately to facilitate debug of boot programs.
1. NRST and NTRST handling in Debug Mode during development.
2. NRST and NTRST handling during production.
Controller
Controller
Reset
Reset
Seperate or Common Reset Management
NTRST
NRST
AT91M42800A
(1)
Figure 7-1
above.
Controller
Reset
AT91M42800A
NTRST
NRST
AT91M42800A
(2)
Figure 7-1
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