M42800A Atmel Corporation, M42800A Datasheet - Page 12

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.5
7.5.1
7.5.2
12
Reset
AT91M42800A
NRST Pin
NTRST Pin
The AT91M42800A microcontroller has a fully static design and works either on the Master
Clock (MCK), generated from the Slow Clock by means of the two integrated PLLs, or on the
Slow Clock (SLCK).
These clocks are also provided as an output of the device on the pin MCKO, which is multi-
plexed with a general-purpose I/O line. While NRST is active, and after the reset, the MCKO is
valid and outputs an image of the SLCK signal. The PIO Controller must be programmed to use
this pin as standard I/O line.
Reset initializes the user interface registers to their default states as defined in the peripheral
sections of this datasheet and forces the ARM7TDMI to perform the next instruction fetch from
address zero. Except for the program counter, the ARM core registers do not have defined reset
states. When reset is active, the inputs of the AT91M42800A must be held at valid logic levels.
The EBI address lines drive low during reset. All the peripheral clocks are disabled during reset
to save power.
NRST is the active low reset input. It is asserted asynchronously, but exit from reset is synchro-
nized internally to the slow clock (SLCK). At power-up, NRST must be active until the on-chip
oscillator is stable. During normal operation, NRST must be active for a minimum of 10 SLCK
clock cycles to ensure correct initialization.
The pins BMS and NTRI are sampled during the 10 SLCK clock cycles just prior to the rising
edge of NRST.
The NRST pin has no effect on the on-chip Embedded ICE logic.
Test Access Port (TAP) reset functionality is provided through the NTRST signal.
The NTRST control pin initializes the selected TAP controller. The TAP controller involved in this
reset is determined according to the initial logical state applied on the JTAGSEL pin after the last
valid NRST.
In either Boundary Scan or ICE Mode, a reset can be performed from the same or different cir-
cuitry, as shown in
signal, must be asserted after each power-up. (See the AT91M42800A Electrical Datasheet,
Atmel Lit. No. 1776, for the necessary minimum pulse assertion time.)
Figure 7-1 on page 13
below. But in all cases, the NTRST like the NRST
1779ES–ATARM–14-Apr-06