M42800A Atmel Corporation, M42800A Datasheet - Page 9

• Manufacturer Part Number: M42800A
• Manufacturer: Atmel Corporation

Specifications of M42800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 54
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

5. Architectural Overview
5.1
5.2
5.2.1
1779ES–ATARM–14-Apr-06
Memories
Peripherals
System Peripherals
The AT91M42800A microcontroller integrates an ARM7TDMI with its embedded ICE interface,
memories and peripherals. Its architecture consists of two main buses, the Advanced System
Bus (ASB) and the Advanced Peripheral Bus (APB). Designed for maximum performance and
controlled by the memory controller, the ASB interfaces the ARM7TDMI processor with the on-
chip 32-bit memories, the External Bus Interface (EBI) and the AMBA
Bridge drives the APB, which is designed for accesses to on-chip peripherals and optimized for
low power consumption.
The AT91M42800A microcontroller implements the ICE port of the ARM7TDMI processor on
dedicated pins, offering a complete, low-cost and easy-to-use debug solution for target
debugging.
The AT91M42800A microcontroller embeds up to 8K bytes of internal SRAM. The internal mem-
ory is directly connected to the 32-bit data bus and is single-cycle accessible. This provides
maximum performance of 30 MIPS at 33 MHz by using the ARM instruction set of the processor.
The on-chip memory significantly reduces the system power consumption and improves its per-
formance over external memory solutions.
The AT91M42800A microcontroller features an External Bus Interface (EBI), which enables con-
nection of external memories and application-specific peripherals. The EBI supports 8- or 16-bit
devices and can use two 8-bit devices to emulate a single 16-bit device. The EBI implements the
early read protocol, enabling faster single clock cycle accesses two times faster than standard
memory interfaces.
The AT91M42800A microcontroller integrates several peripherals, which are classified as sys-
tem or user peripherals. All on-chip peripherals are 32-bit accessible by the AMBA Bridge, and
can be programmed with a minimum number of instructions. The peripheral register set is com-
posed of control, mode, data, status and enable/disable/status registers.
An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs/SPIs
and the on- and off-chip memories without processor intervention. Most importantly, the PDC
removes the processor interrupt handling overhead and significantly reduces the number of
clock cycles required for a data transfer. It can transfer up to 64K continuous bytes without
reprogramming the start address. As a result, the performance of the microcontroller is
increased and the power consumption reduced.
The External Bus Interface (EBI) controls the external memory and peripheral devices via an 8-
or 16-bit data bus and is programmed through the APB. Each chip select line has its own pro-
gramming register.
The Power Management Controller (PMC) optimizes power consumption of the product by con-
trolling the clocking elements such as the oscillator and the two PLLs, system and user
peripheral clocks.
The Advanced Interrupt Controller (AIC) controls the internal sources from the internal peripher-
als and the five external interrupt lines (including the FIQ) to provide an interrupt and/or fast
AT91M42800A
™
Bridge. The AMBA
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