SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 11

• Manufacturer Part Number: SAM9260
• Manufacturer: Atmel Corporation

Specifications of SAM9260

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 210 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

List of Figures
ARM9E-S Technical Reference Manual
ARM DDI 0165B
Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Figure 1-5
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 3-1
Figure 3-2
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 4-6
Figure 4-7
Figure 4-8
Figure 4-9
Figure 4-10
Figure 4-11
Copyright © 2000 ARM Limited. All rights reserved.
Five-stage pipeline ........................................................................ 1-3
The instruction pipeline ................................................................. 1-4
ARM9E-S block diagram ............................................................... 1-7
ARM9E-S core diagram ................................................................ 1-8
ARM9E-S interface diagram ......................................................... 1-9
Big-endian addresses of bytes within words ................................. 2-4
Little-endian addresses of bytes within words .............................. 2-5
Register organization in ARM state ............................................ 2-11
Register organization in Thumb state ......................................... 2-13
Mapping of Thumb state registers onto ARM state registers ...... 2-14
Program status register ............................................................... 2-16
Power-on reset .............................................................................. 3-3
ARM9E-S behavior on exit from reset .......................................... 3-5
Simple memory cycle .................................................................... 4-8
Nonsequential instruction fetch cycle ............................................ 4-9
Sequential instruction fetch cycles .............................................. 4-11
Merged I-S cycle ......................................................................... 4-12
ARM9TDMI effect of DABORT on following memory access ..... 4-19
ARM9E-S aborted data memory access ..................................... 4-20
Data replication ........................................................................... 4-23
Simple memory cycle .................................................................. 4-24
Nonsequential data memory cycle .............................................. 4-26
Back to back memory cycles ...................................................... 4-27
Sequential access cycles ............................................................ 4-28
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