SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 93
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SAM9260
Manufacturer Part Number
SAM9260
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9260.pdf
(802 pages)
5.SAM9260.pdf
(47 pages)
Specifications of SAM9260
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
210 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9260 PDF datasheet #4
- SAM9260 PDF datasheet #5
- Current page: 93 of 290
- Download datasheet (5Mb)
4.8.5
4.8.6
ARM DDI 0165B
DLOCK
DnM[4:0]
DLOCK indicates to an arbiter that an atomic operation is being performed on the bus.
DLOCK is normally LOW, but is set HIGH to indicate that a
is being performed. These instructions perform an atomic read/write operation, and can
be used to implement semaphores.
If DLOCK is asserted in a cycle, then this indicates that there is another access in the
next cycle that must be locked to the first. In the case of a multi-master system, the
ARM processor must not be degranted the bus when a locked transaction is being
performed.
DnM[4:0] indicates the operating mode of the ARM9E-S. This bus corresponds to the
bottom five bits of the CPSR, unless a forced User mode access is being performed, in
which case DnM[4:0] indicates User mode. These bits are inverted with respect to the
CPSR.
Copyright © 2000 ARM Limited. All rights reserved.
SWP
or
SWPB
Memory Interface
instruction
4-17
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