SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 168
SAM9260
Manufacturer Part Number
SAM9260
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9260.pdf
(802 pages)
5.SAM9260.pdf
(47 pages)
Specifications of SAM9260
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
210 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9260 PDF datasheet #4
- SAM9260 PDF datasheet #5
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Instruction Cycle Times
8.3
8-8
Branch and ARM branch with link
Any ARM or Thumb branch, and an ARM branch with link operation takes three
cycles:
1.
2.
3.
Cycle
1
2
3
During the first cycle, a branch instruction calculates the branch destination while
performing a prefetch from the current PC. This prefetch is performed in all case,
because by the time the decision to take the branch has been reached, it is already
too late to prevent the prefetch. If the previous instruction requested a data
memory access, the data is transferred in this cycle.
During the second cycle, the ARM9E-S performs a fetch from the branch
destination. If the link bit is set, the return address to be stored in r14 is calculated.
During the third cycle, the ARM9E-S performs a fetch from the destination + i,
refilling the instruction pipeline.
Copyright © 2000 ARM Limited. All rights reserved.
IA
pc’
pc’ + i
pc’ + 2i
InMREQ,
ISEQ
N cycle
S cycle
S cycle
Table 8-4 Branch and ARM branch with link cycle timings
INSTR
(pc + 2i)
(pc’)
(pc’ + i)
(pc’ + 2i)
DA
-
-
-
DnMREQ,
DSEQ
I cycle
I cycle
I cycle
ARM DDI 0165B
RDATA/
WDATA
-
-
-
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