SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 133

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SAM9M10

Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9M10

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
5.4.2
ARM DDI 0029G
Clock switch during test
When serial test patterns are being applied to the ARM7TDMI core through the JTAG
interface, the processor must be clocked using DCLK, MCLK must be held LOW.
Entry into test is less automatic than debug and you must take care to prevent spurious
clocking on the way into test.
The TAP controller can now be used to serially test the processor. If scan chain 0 and
INTEST are selected, DCLK is generated while the state machine is in the
RUN-TEST/IDLE state. During EXTEST, DCLK is not generated.
On exit from test, RESTART must be selected as the TAP controller instruction. When
this is done, MCLK can be resumed. After INTEST testing, you must take care to
ensure that the core is in a sensible state before reverting to normal operation. The safest
ways to do this is are by using one of the following:
select RESTART, then cause a system reset
insert
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into the instruction pipeline before reverting.
Debug Interface
5-11

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