SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 233

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

B.6.3
B.6.4
ARM DDI 0029G
Instruction register
Scan path select register
Purpose
Length
Operating mode
Purpose
Length
Operating mode
The number of the currently selected scan chain is reflected on the SCREG[3:0]
outputs. The TAP controller can be used to drive external scan chains in addition to
those within the ARM7TDMI macrocell. The external scan chain must be assigned a
number and control signals for it can be derived from SCREG[3:0], IR[3:0],
Copyright © 1994-2001. All rights reserved.
The 32-bit device identification code is loaded into the ID register
from its parallel inputs during the CAPTURE-DR state.
The least significant bit of the register is scanned out first.
Changes the current TAP instruction.
4 bits.
In the SHIFT-IR state, the instruction register is selected as the
serial path between TDI and TDO.
During the UPDATE-IR state, the value in the instruction register
becomes the current instruction.
During the CAPTURE-IR state, the binary value 0001 is loaded
into this register. This value is shifted out during SHIFT-IR. On
reset, IDCODE becomes the current instruction.
The least significant bit of the register is scanned in or out first.
Changes the current active scan chain.
4 bits.
SCAN_N as the current instruction in the SHIFT-DR state selects
the scan path select register as the serial path between TDI and
TDO.
During the CAPTURE-DR state, the value 1000 binary is loaded
into this register. This value is loaded out during SHIFT-DR, while
a new value is loaded in.
During the UPDATE-DR state, the value in the register selects a
scan chain to become the currently active scan chain. All further
instructions, such as INTEST, then apply to that scan chain. The
currently selected scan chain changes only when a SCAN_N
instruction is executed, or when a reset occurs. On reset, scan
chain 0 is selected as the active scan chain.
The least significant bit of the register is scanned in or out first.
Debug in Depth
B-15