ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 152

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

18.7.4
152
Atmel ATmega48PA/88PA/168PA [Preliminary]
Phase Correct PWM Mode
The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dual-slope
operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-
TOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. In
non-inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare
match between TCNT2 and OCR2x while upcounting, and set on the compare match while
downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope
operation has lower maximum operation frequency than single slope operation. However, due
to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor
control applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP.
When the counter reaches TOP, it changes the count direction. The TCNT2 value will be
equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode
is shown on
illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM
outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches
between OCR2x and TCNT2.
Figure 18-7. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOT-
TOM value.
TCNTn
OCnx
OCnx
Period
Figure
18-7. The TCNT2 value is in the timing diagram shown as a histogram for
1
2
3
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
(COMnx1:0 = 2)
(COMnx1:0 = 3)
9223B–AVR–09/11