ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 176

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

20. USART0
20.1
20.2
176
Features
Overview
Atmel ATmega48PA/88PA/168PA [Preliminary]
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The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device.
The USART0 can also be used in Master SPI mode, see “USART in SPI Mode” on page 202.
The Power Reduction USART bit, PRUSART0, in
42
A simplified block diagram of the USART Transmitter is shown in
CPU accessible I/O Registers and I/O pins are shown in bold.
The dashed boxes in the block diagram separate the three main parts of the USART (listed
from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all
units. The Clock Generation logic consists of synchronization logic for external clock input
used by synchronous slave operation, and the baud rate generator. The XCKn (Transfer
Clock) pin is only used by synchronous transfer mode. The Transmitter consists of a single
write buffer, a serial Shift Register, Parity Generator and Control logic for handling different
serial frame formats. The write buffer allows a continuous transfer of data without any delay
between frames. The Receiver is the most complex part of the USART module due to its clock
and data recovery units. The recovery units are used for asynchronous data reception. In addi-
tion to the recovery units, the Receiver includes a Parity Checker, Control logic, a Shift
Register and a two level receive buffer (UDRn). The Receiver supports the same frame for-
mats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors.
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
must be disabled by writing a logical zero to it.
“Minimizing Power Consumption” on page
Figure 20-1 on page
9223B–AVR–09/11
177.