AD7262 Analog Devices, AD7262 Datasheet
AD7262
Specifications of AD7262
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AD7262 Summary of contents
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... The AD7262/AD7262-5 are dual, 12-bit, high speed, low power, successive approximation ADCs that operate from a single 5 V power supply. The AD7262 features throughput rates MSPS per on-chip ADC. The AD7262-5 features throughput rates 500 kSPS. Two complete ADC functions allow simultaneous sampling and conversion of two channels ...
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... Power-Down Modes .................................................................. 22 Control Register ......................................................................... 23 On-Chip Registers ...................................................................... 24 Serial Interface ................................................................................ 25 Calibration ....................................................................................... 27 Internal Offset Calibration ........................................................ 27 Adjusting the Offset Calibration Registers ................................. 28 System Gain Calibration............................................................ 28 Microprocessor Interfacing ........................................................... 29 AD7262/AD7262-5 to ADSP-BF53x ....................................... 29 Application Hints ........................................................................... 30 Grounding and Layout .............................................................. 30 PCB Design Guidelines for LFCSP .......................................... 30 Outline Dimensions ....................................................................... 31 Ordering Guide .......................................................................... 31 Rev Page ...
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... DC Leakage Current 3 Input Capacitance Output Impedance REF REF Reference Temperature Coefficient 3 V Noise REF DRIVE = 20 MHz for AD7262- 2.5 V internal/external; T REF Min Typ Max −85 −77 2 −97 3 −76 −90 1.2 1.7 12 ±0.5 ±1 ± ...
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... Rev Page Unit Test Conditions/Comments V V μ DRIVE μ MSPS AD7262 kSPS AD7262 25°C to 105°C only A mV μV/°C All comparators 2 GΩ ...
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... V /2) of the AD7262, the V voltage should be dropped to lie within a range from 1. 2. REF CM per comparator is the specified value divided by two. DD Rev Page AD7262 Unit Test Conditions/Comments Digital inputs = DRIVE ...
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... Description 2 AD7262 AD7262 2 AD7262 1/f SCLK SCLK AD7262 AD7262-5 Minimum time between end of serial read/bus relinquish and next falling edge SCLK setup time th Delay from 19 SCLK falling edge until D three-state disabled Data access time after SCLK falling edge SCLK to data valid hold time ...
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... CC other conditions above those indicated in the operational CC section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION + 0 0.3 V DRIVE + 0 0.3 V DRIVE 0 Rev Page AD7262 ...
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... SCLK Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7262/AD7262-5. This clock is also used as the clock source for the conversion process. A minimum of 31 clocks is required to perform the conversion and access the 12-bit result. ...
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... Serial Data Outputs. The data output from the AD7262/AD7262-5 is supplied to each pin as a serial OUT OUT data stream in twos complement format. The bits are clocked out on the falling edge of the SCLK input. A total of 31 SCLKs is required to perform the conversion and access the 12-bit data. During ...
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... AD7262 TYPICAL PERFORMANCE CHARACTERISTICS 0 DRIVE f = 1MSPS S 0 25°C A INTERNAL REFERENCE PGA GAIN = 2 0.2 0 –0.2 –0.4 –0.6 0 500 1000 1500 2000 2500 CODE Figure 5. Typical DNL at Gain of 2 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0 DRIVE –0 1MSPS 25°C A –0.8 INTERNAL REFERENCE PGA GAIN = 2 – ...
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... INTERNAL REFERENCE 600 GAIN Figure 15 Bandwidth vs. Gain DRIVE f = 1MSPS S 35 INTERNAL REFERENCE F = 100kHz PGA GAIN AD7262 160 180 200 64 96 128 64 96 128 ...
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... AD7262 –90 –88 –86 –84 –82 –80 –78 –76 AV – –72 INTERNAL REFERENCE f RIPPLE – GAIN Figure 17. Common-Mode Rejection vs. Gain –80 –79 –78 –77 –76 –75 –74 – DRIVE – RIPPLE –71 GAIN = 2 INTERNAL REFERENCE – ...
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... OUT C C/C D SINK CURRENT OUT OUT 200 D SINK CURRENT OUT 100 0 –100 D SOURCE CURRENT OUT –200 C A/C B SOURCE CURRENT OUT OUT C C/C D SOURCE CURRENT OUT OUT –300 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 CURRENT (mA) Figure 23. D and C Source and Sink Current OUT OUT 2.0 2.2 2.4 1.9 2.1 2.3 2.5 Rev Page AD7262 ...
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... N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6. 1. Thus for a 12-bit converter, this is 86 dB. Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. For the AD7262/AD7262- defined as = THD (dB) 20 log ...
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... Each ADC in the AD7262/AD7262-5 has two high impedance differential analog inputs. Figure 24 shows the equivalent circuit of the analog input structure of the AD7262/AD7262-5. It consists of a fully differential input amplifier that buffers the analog input signal and provides the gain selected by using the gain pins or the control register ...
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... The AD7262/AD7262-5 output is twos complement, and the ideal transfer characteristic is shown in Figure 25. The designed code transitions occur at successive integer LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is dependent on the analog input range selected. The LSB size for the AD7262/AD7262 shown in the following equation: OUT × ...
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... DGND pin is connected to the digital ground plane of the system. The analog inputs on the AD7262/AD7262-5 are true differen- tial and have an input impedance in excess of 1 GΩ; thus, no driving op amps are required. The AD7262/AD7262-5 can operate with either an internal or an external reference ...
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... THESE CAPACITORS ARE PLACED AT THE SUPPLY SOURCE AND MAY NOT BE REQUIRED IN ALL SYSTEMS. 2 THIS SUPPLY CAN BE CONNECTED TO THE ANALOG 5V SUPPLY IF REQUIRED. Figure 26. Typical Connection Diagram for the AD7262/AD7262-5 in Control Register Mode (All Gain Pins Tied to Ground) Configured for a PGA Gain of 2 +5V 100nF 1 10µ ...
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... THESE CAPACITORS ARE PLACED AT THE SUPPLY SOURCE AND MAY NOT BE REQUIRED IN ALL SYSTEMS. 2 THIS SUPPLY CAN BE CONNECTED TO THE ANALOG 5V SUPPLY IF REQUIRED. Figure 27. Typical Connection Diagram for the AD7262/AD7262-5 in Pin-Driven Mode with Gain of 2 and Both ADCs and Comparators Fully Powered On 100nF 1 10µ ...
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... Hall effect sensors . CC or the inner tracks from an optical encoder. Figure 29 shows how the AD7262/AD7262-5 can be used in a typical application. An optical encoder is shown in Figure 29, but other sensor types could as easily be used. Figure 29 indicates a typical application configuration only, and there are several other configurations that render equally effective results MΩ ...
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... OUTPUT SUCCESSIVE T/H PGA APPROXIMATION DRIVERS ADC BUF OUTPUT DRIVERS COMP OUTPUT DRIVERS COMP OUTPUT DRIVERS COMP OUTPUT DRIVERS COMP AGND DGND Rev Page AD7262 D A OUT SCLK CAL CS REFSEL DRIVE D B OUT PD0/D IN PD1 PD2 C A OUT ...
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... PD2 = PD1 = PD0 = 1 resets the AD7262/AD7262-5 when in pin-driven mode only. The AV CC the AD7262/AD7262-5 when the comparators are powered up but the ADCs are powered-down. External diodes can be used from the C V supplies to ensure they retain a supply at all instances. ...
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... ADCs. It takes 15 μs to power up the AD7262/AD7262-5 when using an external reference. When the internal reference is used, 240 μs are required to power up the AD7262/AD7262-5 with a 1 μF decoupling capacitor. CONTROL REGISTER The control register on the AD7262/AD7262 12-bit read and write register, which is used to control the device when not in pin-driven mode ...
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... ADC, and two external gain registers for storing the gain error. The control register and the offset and gain registers are read and write registers. On power-up, all registers in the AD7262/AD7262-5 are set to 0. Addressing the On-Chip Registers Writing to a Register ...
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... SCLK edge after the data has been clocked out, as illustrated in Figure 35. A throughput rate of 1 MSPS can still be achieved for the AD7262 when a 32 MHz SCLK frequency is used. The remaining data is then clocked out by subsequent SCLK falling edges. When using a 32 MHz or ...
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... AD7262 FIRST DATA BIT CLOCKED OUT ON THE SCLK OUT THREE-STATE D B OUT THREE-STATE Figure 33. Serial Interface Timing Diagram When Reading Data on the SCLK D A OUT THREE-STATE Figure 34. Reading Data from Both ADCs on One D FIRST DATA BIT CLOCKED ...
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... This is the maximum removable offset for PGA gain ≥ 32 Figure 36. Calibration Timing Diagram Rev Page which is 5/4096 or 1.22 mV for the AD7262/ BITs . × 128 LSB Gain Maximum Removable Offset Voltage ±156.16 mV ±78.08 mV ±52.053 mV 1 ± ...
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... The gain calibration feature can be used to implement accurate gain matching between ADC A and ADC B. The system calibration function is used by setting the sensors to which the AD7262/AD7262-5 are connected gain state. The AD7262/AD7262-5 convert this analog input to a digital A output code, which corresponds to the system gain and is avail- ...
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... DSPs means only one serial port is necessary to read from both D pins simultaneously. Figure 37 shows both D OUT the AD7262/AD7262-5 connected to Serial Port 0 of OUT the ADSP-BF53x. The SPORT0 Receive Configuration 1 register and SPORT0 Receive Configuration 2 register should be set up as outlined in Table 14 and Table 15. ...
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... However, the analog ground plane should be allowed to run under the AD7262/AD7262-5 to avoid noise coupling. The power supply lines to the AD7262/ AD7262-5 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. ...
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... AD7262BCPZ-5 −40°C to +105°C AD7262BCPZ-5-RL7 1 −40°C to +105°C 1 AD7262BSTZ −40°C to +105°C 1 AD7262BSTZ-RL7 −40°C to +105°C 1 AD7262BSTZ-5 −40°C to +105°C 1 AD7262BSTZ-5-RL7 −40°C to +105°C 1 EVAL-AD7262EDZ 1 EVAL-CED1Z RoHS Compliant Part. 0.60 MAX 0.60 MAX ...
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... AD7262 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07606-0-7/08(0) Rev Page ...