AD7262 Analog Devices, AD7262 Datasheet - Page 23

• Manufacturer Part Number: AD7262
• Description: 1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators
• Manufacturer: Analog Devices

Specifications of AD7262

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,5V p-p
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

Power-Up Conditions
On power-up, the status of the gain pins determine which mode
of operation is selected, as outlined in the Gain Selection section.
All registers are set to 0 by default.
If the AD7262/AD7262-5 are powered up in pin-driven mode,
the gain pins and the PDx pins should be configured to the
appropriate logic states and a calibration initiated if required.
Alternatively, if the AD7262/AD7262-5 are powered up in
control register mode, the comparators and ADCs are powered
down and the default gain is 1. Thus, powering up in control
register mode requires a write to the device to power up the
comparators and the ADCs.
It takes 15 μs to power up the AD7262/AD7262-5 when using
an external reference. When the internal reference is used, 240 μs
are required to power up the AD7262/AD7262-5 with a 1 μF
decoupling capacitor.
CONTROL REGISTER
The control register on the AD7262/AD7262-5 is a 12-bit read
and write register, which is used to control the device when not
in pin-driven mode. The PD0/D
D
0 (that is, the part is not in pin-driven mode). The control
register can be used to select the gain of the PGAs, the power-
down modes, and the calibration of the offset for both ADC A
and ADC B. When operating in the control register mode, PD1
and PD2 should be connected to a low logic state.
Table 8. Control Register Bits
MSB
Bit 11
RD3
Table 9. Control Register Bit Function Description
Bits
11 to 8
7
6 to 4
3 to 0
Table 10. Write Address Bits
WR3
0
IN
pin for the AD7262/AD7262-5 when the gain pins are set to
PD0/D
D
SCLK
OUT
CS
IN
A
Mnemonic
RD3 to RD0
CAL
PD2 toPD0
G3 to G0
Bit 10
RD2
WR3
1
WR2
0
t
2
WR2
2
THREE-STATE
Bit 9
RD1
WR1
Description
Register address bits. These bits select which register the subsequent read is from. See Table 11.
Setting this bit high initiates an internal offset calibration. Once the calibration is completed, this pin can be reset low,
and the internal offset, which is stored in the on-chip offset registers, is automatically removed from the ADC results.
Power-down bits. These bits select which power-down mode is programmed. See Table 7.
Gain selection bits. These bits select which gain setting is used on the front-end PGA. See Table 6.
3
WR0
4
IN
RD3
pin serves as the serial
Bit 8
RD0
WR1
0
5
t
13
RD2
Figure 30. Timing Diagram for a Write Operation to the Control Register
6
RD1
7
Bit 7
CAL
RD0
t
14
8
CAL
WR0
1
9
PD2
Bit 6
PD2
10
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PD1
11
PD0
12
Bit 5
PD1
Read Register Addressed
Control register
G3
These functions can also be implemented by setting the logic
levels on the gain pins, the power-down pins, and the CAL pin,
respectively. The control register can also be used to read the
offset and gain registers.
Data is loaded from the PD0/D
on the falling edge of SCLK when CS is in a logic low state. The
control register is selected by first writing the appropriate four
WR bits, as outlined in
clocked into the control register of the device. Thus, on the 16
falling SCLK edge, the LSB is clocked into the device. One more
SCLK cycle is then required to write to the internal device
registers. In total, 17 SCLK cycles are required to successfully
write to the AD7262/AD7262-5. The data is transferred on the
PD0/D
The data transferred on the D
AD7262-5 configuration for the next conversion.
Only the information provided on the 12 falling clock edges
after the CS falling edge and the initial four write address bits is
loaded to the control register. The PD0/D
logic low state for the four bits RD3 to RD0 when using the
control register to select the power-down modes or gain setting
or when initializing a calibration. The RD bits should also be set
to a logic low level to access the ADC results from both D
and D
The power-up status of all bits is 0 and the MSB denotes the first
bit in the data stream. The bit functions are outlined in Table 8
and Table 9.
13
G2
14
OUT
IN
G1
Bit 4
PD0
15
line while the conversion result is being processed.
B.
G0
16
17
Bit 3
G3
18
Table 10
THREE-STATE
19
DB11
IN
line corresponds to the AD7262/
IN
20
. The 12 data bits must then be
Bit 2
G2
DB10
pin of the AD7262/AD7262-5
30
IN
pin should have a
Bit 1
G1
DB0
31
THREE-
STATE
t
QUIET
AD7262
LSB
Bit 0
G0
t
8
OUT
A
th