AD7262 Analog Devices, AD7262 Datasheet - Page 16

• Manufacturer Part Number: AD7262
• Description: 1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators
• Manufacturer: Analog Devices

Specifications of AD7262

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,5V p-p
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7262
The two diodes provide ESD protection. Care must be taken to
ensure that the analog input signals never exceed the supply rails
by more than 300 mV. Exceeding 300 mV causes these diodes to
become forward-biased and to start conducting current into the
substrate. These diodes can conduct up to 10 mA without
causing irreversible damage to the part. The C1 capacitors in
Figure 24 are typically 5 pF and can primarily be attributed to
pin capacitance.
The AD7262/AD7262-5 can accept differential analog inputs from
Table 5 details the analog input range for the AD7262/AD7262-5
for the various PGA gain settings. Here, V
2.5 V (AV
Table 5. Analog Input Range for Various PGA Gain Settings
PGA Gain Setting
1
2
3
4
6
8
12
16
24
32
48
64
96
128
1
For V
to 3.4 V.
V
CM
CM
= 2 V. If V
−
CC
V
V
⎛
⎜
⎝
/2, with AV
IN
IN
2
+
–
V
×
CM
C1
C1
Gain
REF
= AV
Figure 24. Analog Input Structure
CC
⎞
⎟
⎠
V
V
/2, the analog input range for V
Analog Input Range for V
0.75 V to 3.25 V
1.875 V to 3.125 V
2.083 V to 2.916 V
2.187 V to 2.813 V
2.292 V to 2.708 V
2.344 V to 2.656 V
2.396 V to 2.604 V
2.422 V to 2.578 V
2.448 V to 2.552 V
2.461 V to 2.539 V
2.474 V to 2.526 V
2.480 V to 2.520 V
2.487 V to 2.513 V
2.490 V to 2.510 V
DD
DD
CC
to
= 5 V).
V
CM
AMP
AMP
+
⎛
⎜
⎝
2
V
×
Gain
1
REF
REF
⎞
⎟
⎠
= 2.5 V and V
V
V
OUT
OUT
IN
+
–
IN
+ and V
+ and V
IN
− is 1.6 V
IN
CM
−
Rev. 0 | Page 16 of 32
=
When a full-scale step input is applied to either differential input
on the AD7262/AD7262-5 while the other analog input is held
at a constant voltage, 3 μs of settling time is typically required
prior to capturing a stable digital output code.
Transfer Function
The AD7262/AD7262-5 output is twos complement, and the
ideal transfer characteristic is shown in Figure 25. The designed
code transitions occur at successive integer LSB values (that is,
1 LSB, 2 LSB, and so on). The LSB size is dependent on the analog
input range selected. The LSB size for the AD7262/AD7262-5 is
shown in the following equation:
V
The AD7262/AD7262-5 have a V
voltage at which the serial interface operates. V
ADC and the comparators to easily interface to both 3 V and
5 V processors. For example, when the AD7262/AD7262-5 are
operated with AV
a 3 V supply, allowing a large analog input range with low voltage
digital processors.
DRIVE
NOTES
1. FULL-SCALE RANGE (FSR) = V
2
×
000...001
000...000
100...010
100...001
100...000
011...110
011...111
111...111
⎛
⎜
⎜
⎜
⎜
⎜
⎝
⎛
⎜
⎝
(V
V
CM
CM
Figure 25. Twos Complement Transfer Function
– (FSR/2)) + 1LSB
+
0V
⎛
⎜
⎝
2
CC
V
×
= 5 V, the V
Gain
REF
⎞
⎟
⎠
4096
⎞
⎟
⎠
−
⎛
⎜
⎝
ANALOG INPUT
IN
V
+ – V
CM
DRIVE
DRIVE
−
IN
(V
–.
⎛
⎜
⎝
pin can be powered from
2
CM
feature to control the
V
×
+ (FSR/2)) – 1LSB
Gain
REF
⎞
⎟
⎠
⎞
⎟
⎠
DRIVE
⎞
⎟
⎟
⎟
⎟
⎟
⎠
allows the