AD7262 Analog Devices, AD7262 Datasheet - Page 6

• Manufacturer Part Number: AD7262
• Description: 1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators
• Manufacturer: Analog Devices

Specifications of AD7262

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,5V p-p
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7262
TIMING SPECIFICATIONS
AV
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
TIMING DIAGRAM
SCLK
CONVERT
QUIET
2
3
4
5
6
7
8
9
10
11
12
13
14
POWER-UP
Sample tested during initial release to ensure compliance. All input signals are specified with t
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the
Terminology section.
See the Serial Interface section.
The time required for the output to cross 0.4 V or 2.4 V.
3
CC
= 4.75 V to 5.25 V, C
D
D
SCLK
OUT
OUT
CS
A
B
2.7 V ≤ V
200
40
32
20
19 × t
475
950
13
10
15
29
15
0.4 × t
0.4 × t
13
13
5
35
2
2
3
3
240
15
SCLK
SCLK
SCLK
1
t
2
DRIVE
A
≤ 3.6 V
_C
2
Limit at T
B
THREE-STATE
THREE-STATE
V
CC
3
= C
C
MIN
4.75 V ≤ V
200
40
32
20
19 × t
475
950
13
10
15
23
13
0.4 × t
0.4 × t
13
13
5
35
2
2
3
3
240
15
_C
4
, T
D
V
MAX
SCLK
SCLK
SCLK
CC
5
= 2.7 V to 5.25 V, V
DRIVE
Figure 2. Serial Interface Timing Diagram
≤ 5.25 V
18
t
3
Rev. 0 | Page 6 of 32
19
DB11
DB11
Unit
kHz min
MHz max
MHz typ
MHz max
ns max
ns max
ns max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns min
ns max
μs min
μs min
ns min
ns min
μs max
μs max
REF
A
B
20
t
7
= 2.5 V internal/external; T
DB10
DB10
t
4
A
B
21
R
DB9
DB9
t
6
= t
Description
AD7262
AD7262
AD7262-5
t
AD7262
AD7262-5
Minimum time between end of serial read/bus relinquish
and next falling edge of CS
CS to SCLK setup time
Delay from 19
three-state disabled
Data access time after SCLK falling edge
SCLK to data valid hold time
SCLK high pulse width
SCLK low pulse width
CS rising edge to falling edge pulse width
CS rising edge to D
relinquish
SCLK falling edge to D
SCLK falling edge to D
Minimum CAL pin high time
Minimum time between the CAL pin high and the CS
falling edge
D
D
Internal reference, with a 1 μF decoupling capacitor
With an external reference, 10 μs typical
SCLK
IN
IN
A
B
F
= 5 ns (10% to 90% of AV
setup time prior to SCLK falling edge
hold time after SCLK falling edge
= 1/f
t
5
2
2
SCLK
th
SCLK falling edge until D
A
29
OUT
= T
DB1
DB1
A, D
OUT
OUT
MIN
A
B
CC
A, D
A, D
) and timed from a voltage level of 1.6 V.
30
OUT
to T
B, high impedance/bus
OUT
OUT
DB0
DB0
MAX
B, high impedance
B, high impedance
31
t
9
A
B
, unless otherwise noted.
THREE-
STATE
THREE-
STATE
t
OUT
QUIET
t
A and D
8
OUT
B are
1