AD7262 Analog Devices, AD7262 Datasheet - Page 22

• Manufacturer Part Number: AD7262
• Description: 1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators
• Manufacturer: Analog Devices

Specifications of AD7262

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,5V p-p
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7262
MODES OF OPERATION
The AD7262/AD7262-5 allow the user to choose between two
modes of operation, pin-driven mode and control register mode.
PIN-DRIVEN MODE
In pin-driven mode, the user can select the gain of the PGA, the
power-down mode, internal or external reference, and initiate
a calibration of the offset for both ADC A and ADC B. These
functions are implemented by setting the logic levels on the gain
pins (G3 to G0), the power-down pins (PD2 to PD0), the REFSEL
pin, and the CAL pin, respectively.
The logic state of Pin G3 to Pin G0 determines which mode of
operation is selected. Pin-driven mode is selected if at least one
of the gain pins is set to a logic high state. Alternatively, if all
four gain pins are connected to a logic low, the control register
mode of operation is selected.
GAIN SELECTION
The on-board PGA allows the user to select from 14 program-
mable gain stages: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32,
×48, ×64, ×96, and ×128. The PGA accepts fully differential
analog signals and provides three key functions, which include
selecting gains for small amplitude input signals, driving the
ADCs switched capacitive load, and buffering the source from
the switching effects of the SAR ADCs. The AD7262/AD7262-5
offer the user great flexibility in user interface, providing gain
selection via the control register or by driving the gain pins to
the desired logic state. The AD7262/AD7262-5 have four gain
pins, G3, G2, G1 and G0, as shown in Figure 3. Each gain setting
is selected by setting up the appropriate logic state on each of
the four gain pins, as outlined in Table 6. If all four gain pins are
connected to a logic low level, the part is put in control register
mode and the gain settings are selected via the control register.
Table 6. Gain Selection
G3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
G2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
G1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
G0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Software control
via control register
1
2
3
4
6
8
12
16
24
32
48
64
96
128
Gain
Rev. 0 | Page 22 of 32
POWER-DOWN MODES
The AD7262/AD7262-5 offer the user a number of power-down
options to enable individual device components to be powered
down independently. These options can be chosen to optimize
the power dissipation for different application requirements.
The power-down modes can be selected by either programming
the device via the control register or by driving the PD pins to
the appropriate logic levels. By setting the PD pins to a logic low
level when in pin-driven mode, all four comparators and both
ADCs can be powered down. The PD2 and PD0 pins must be
set to logic high and the PD1 pin set to logic low to power up all
circuitry on the AD7262/AD7262-5. The PD pin configurations
for the various power-down options are outlined in Table 7.
Table 7. Power-Down Modes
PD2
0
0
0
0
1
1
1
1
The AV
the AD7262/AD7262-5 when the comparators are powered up
but the ADCs are powered-down. External diodes can be used
from the C
V
The AD7262/AD7262-5 can be reset in pin-driven mode only
by setting the PDx pins to a logic high state. When the device is
reset, all the registers are cleared and the four comparators and
the two ADCs are left powered down.
In normal mode of operation with the ADCs and comparators
powered on, the C
supply can be at different voltage levels, as indicated in Table 1.
When the comparators on the AD7262/AD7262-5 are in power-
down mode, and the C
potential 0.3 V greater than or less than the AV
supplies consume more current than would be the case if both
sets of supplies were at the same potential. This configuration
does not damage the AD7262/AD7262-5 but results in additional
current flowing in any or all of the AD7262/AD7262-5 supply
pins. This is due to ESD protection diodes within the device. In
applications where power consumption in power-down mode is
critical, it is recommended that the C
and the AV
PD2 = PD1 = PD0 = 1 resets the AD7262/AD7262-5 when in pin-driven mode
only.
1
DRIVE
supplies to ensure they retain a supply at all instances.
PD1
0
0
1
1
0
0
1
CC
1
and V
A
CC
_C
supply be held at the same potential.
PD0
0
1
0
1
0
1
1
B
1
V
DRIVE
CC
A
_C
and/or C
Comparator A,
Comparator B
Off
Off
Off
On
On
On
Off
supplies must continue to be supplied to
B
A
V
_C
CC
B
/C
V
C
C
CC
_C
_C
/C
D
D
C
V
V
_C
CC
A
CC
_C
D
to both the AV
supply and the AV
Comparator C,
Comparator D
Off
Off
On
Off
On
On
Off
V
B
CC
V
CC
supplies are at a
/C
C
CC
_C
supply, the
D
V
CC
CC
and the
supply
ADC A,
ADC B
Off
On
Off
Off
Off
On
Off
CC