AD9122 Analog Devices, AD9122 Datasheet - Page 28

• Manufacturer Part Number: AD9122
• Manufacturer: Analog Devices

Specifications of AD9122

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9122
Register
Name
HB3 Control
Chip ID
FTW LSB
FTW
FTW
FTW MSB
NCO Phase
Offset LSB
NCO Phase
Offset MSB
NCO FTW
Update
I Phase Adj
LSB
I Phase Adj
MSB
Q Phase Adj
LSB
Q Phase Adj
MSB
I DAC Offset
LSB
I DAC Offset
MSB
Address
(Hex)
0x1E
0x1F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x38
0x39
0x3A
0x3B
0x3C
0x3D
Bits
[6:1]
0
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
5
4
1
0
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
[7:0]
Name
HB3[5:0]
Bypass HB3
Chip ID[7:0]
FTW[7:0]
FTW[15:8]
FTW[23:16]
FTW[31:24]
NCO Phase Offset[7:0]
NCO Phase Offset[15:8]
FRAME FTW acknowledge
FRAME FTW request
Update FTW acknowledge
Update FTW request
I Phase Adj[7:0]
I Phase Adj[9:8]
Q Phase Adj[7:0]
Q Phase Adj[9:8]
I DAC Offset[7:0]
I DAC Offset[15:8]
Rev. B | Page 28 of 60
Modulation mode for I Side Half-Band Filter 3.
000000 = input signal not modulated; filter pass band is
from −0.2 to +0.2 of f
001001 = input signal not modulated; filter pass band is
from 0.05 to 0.45 of f
010010 = input signal not modulated; filter pass band is
from 0.3 to 0.7 of f
011011 = input signal not modulated; filter pass band is
from 0.55 to 0.95 of f
100100 = input signal modulated by f
from 0.8 to 1.2 of f
101101 = input signal modulated by f
from 1.05 to 1.45 of f
110110 = input signal modulated by f
from 1.3 to 1.7 of f
111111 = input signal modulated by f
from 1.55 to 1.95 of f
1 = bypass the third-stage interpolation filter.
This register identifies the device as an AD9122.
See Register 0x33.
See Register 0x33.
See Register 0x33.
FTW[31:0] is the 32-bit frequency tuning word that deter-
mines the frequency of the complex carrier generated by the
on-chip NCO. The frequency is not updated when the FTW
registers are written. The values are only updated when Bit 0
of Register 0x36 transitions from 0 to 1.
See Register 0x35.
The NCO sets the phase of the complex carrier signal when
the NCO is reset. The phase offset spans from 0° to 360°.
Each bit represents an offset of 0.0055°. This value is in
twos complement format.
1 = the NCO has been reset due to an extended FRAME
pulse signal.
0 = the NCO is reset on the first extended FRAME pulse after
this bit is set to 1.
1 = the FTW has been updated.
The FTW is updated on the 0-to-1 transition of this bit.
See Register 0x39.
I Phase Adj[9:0] is used to insert a phase offset between
the I and Q datapaths. This offset can be used to correct
for phase imbalance in a quadrature modulator. See the
Quadrature Phase Correction section for more information.
See Register 0x3B.
Q Phase Adj[9:0] is used to insert a phase offset between
the I and Q datapaths. This offset can be used to correct
for phase imbalance in a quadrature modulator. See the
Quadrature Phase Correction section for more information.
See Register 0x3D.
I DAC Offset[15:0] is a value that is added directly to the
samples written to the I DAC.
Description
IN3
IN3
IN3
.
.
.
IN3
IN3
IN3
IN3
IN3
.
.
.
.
.
IN3
IN3
IN3
IN3
; filter pass band is
; filter pass band is
; filter pass band is
; filter pass band is
Default
000000
0
00001000
00000000
00000000
00000000
00000000
00000000
00000000
0
0
0
0
00000000
00
00000000
00
00000000
00000000